Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.

A method of forming a representative part correlating to an actual part. The method includes receiving an actual part design, analyzing the actual part design to identify one or more design elements, based on the one of more design elements; generating a representative part design incorporating the one or more design elements and having a differing overall shape comparative to the actual part design, and forming a representative part based on representative part design. A representative part correlating to an actual part includes one or more design elements of the actual part and a different overall shape relative to the actual part. A method of qualifying an additive manufacturing system or process for forming an actual part.

Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.

In an information processing device according to the present invention, a statistics estimation unit estimates a value of a state quantity by using a statistical model constructed based on values of past state quantities of a target device. A physical estimation unit estimates a value of a state quantity by using a physical model constructed based on design data of the target device. A specification unit specifies a value to be used to manage the target device from the value estimated by the statistics estimation unit and the value estimated by the physical estimation unit based on deterioration of the target device with time.

An apparatus, a recording medium, and a method for generating a control parameter of a screen printer are disclosed. The apparatus includes a memory that stores a simulation model configured to derive predictive inspection information on a printed state of solder paste based on a plurality of control parameters of the screen printer; a communication circuit configured to receive first inspection information on a plurality of solder pastes printed by the screen printer based on a first control parameter, and a processor electrically connected to the memory and the communication circuit. The processor obtains first predictive inspection information by applying the first control parameter to the simulation model, generates a plurality of candidate control parameters based on the first predictive inspection information, determines a plurality of second control parameters among the candidate control parameters, and transmits the plurality of second control parameters to the screen printer via the communication circuit.

In an information processing device according to the present invention, a statistics estimation unit estimates a value of a state quantity by using a statistical model constructed based on values of past state quantities of a target device. A physical estimation unit estimates a value of a state quantity by using a physical model constructed based on design data of the target device. A specification unit specifies a value to be used to manage the target device from the value estimated by the statistics estimation unit and the value estimated by the physical estimation unit based on deterioration of the target device with time.

Partial reconfiguration of a programmable integrated circuit can include loading, using computer hardware, a platform design including a module black-box instance corresponding to a user design and marking, using the computer hardware, data of the platform design including data relating to synchronous boundary crossings between the platform design and the module black-box instance and implementation data for the platform design within an extended routing region available for routing the user design. Unmarked data can be removed from the platform design resulting in a shell circuit design. The user design can be implemented based on the shell circuit design and timing constraints corresponding to the marked data in the shell circuit design.

Partial reconfiguration of a programmable integrated circuit can include loading, using computer hardware, a platform design including a module black-box instance corresponding to a user design and marking, using the computer hardware, data of the platform design including data relating to synchronous boundary crossings between the platform design and the module black-box instance and implementation data for the platform design within an extended routing region available for routing the user design. Unmarked data can be removed from the platform design resulting in a shell circuit design. The user design can be implemented based on the shell circuit design and timing constraints corresponding to the marked data in the shell circuit design.

An apparatus, a recording medium, and a method for generating a control parameter of a screen printer are disclosed. The apparatus includes a memory that stores a simulation model configured to derive predictive inspection information on a printed state of solder paste based on a plurality of control parameters of the screen printer; a communication circuit configured to receive first inspection information on a plurality of solder pastes printed by the screen printer based on a first control parameter, and a processor electrically connected to the memory and the communication circuit. The processor obtains first predictive inspection information by applying the first control parameter to the simulation model, generates a plurality of candidate control parameters based on the first predictive inspection information, determines a plurality of second control parameters among the candidate control parameters, and transmits the plurality of second control parameters to the screen printer via the communication circuit.

A module for predicting semiconductor physical defects includes a defect diagnosis unit used to detect at least one failure circuit in a semiconductor circuit structure; an information acquisition unit used for obtaining a semiconductor mask layout for forming the semiconductor circuit structure, and obtaining a failure path configuration diagram corresponding to the failure circuits and the location information corresponding to the failure path configuration diagram; a feature classification unit used for extracting a plurality of cutting images of the failure path configuration diagram, and performing feature classification on these cutting images to obtain a plurality of image groups; and a failure risk assessment unit used for performing a risk pre-assessment to select at least one high-risk group therefrom, and performing a failure risk analysis to predict at least one high failure risk position in the semiconductor mask layout according to the analysis results and the location information.