A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.

A magnetic memory device includes a magnetic body having magnetic anisotropy and an insulator including a ferromagnetic element. The magnetic body is structurally connected to both ends of the ferromagnetic insulator, and the magnetic body and the ferromagnetic insulator form a ring shape. An easy axis of the magnetic body is directed in a direction parallel to an opening surface of the ring shape in a whole of the magnetic body.

A system and method for storing information in a quantum computer using a quantum storage ring. The method comprises cooling ions in the quantum storage ring to a low temperature; and binding the ions into a lattice structure, forming an ion Coulomb crystal.

Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

Described is an interconnect which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a second magnetoelectric material layer coupled to the ferromagnetic layer, wherein the ferromagnetic layer extends from the first end to the second end. Described is a majority gate device which comprises: a ferromagnetic layer; and first, second, third, and fourth magnetoelectric material layers coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a tunnel junction device coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first terminal coupled to a tunneling junction device; a second terminal coupled to a layer coupling the tunneling junction device and a magnetoelectric device; and a third terminal coupled to the magnetoelectric device.

A measurement system is provided that performs a qualified store algorithm. When performing the algorithm, the measurement system stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.

A measurement system is provided that performs a qualified store algorithm. When performing the algorithm, the measurement system stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.