Disclosed are ferroelectric devices including devices for performing a multiplication of analog input signals and resonators. In one aspect, a ferroelectric nanoelectromechanical device includes a first structural beam, a first input electrode disposed on a first top portion of the first structural beam, and an output electrode. The apparatus further includes a first ferroelectric film disposed on a second top portion of the first input electrode, and a first resistive layer disposed on a third top portion of the first ferroelectric film, wherein a first electrode is positioned at a first end of the first resistive layer and a second electrode is positioned at a second end of the first resistive layer.

Disclosed are ferroelectric devices including devices for performing a multiplication of analog input signals and resonators. In one aspect, a ferroelectric nanoelectromechanical device includes a first structural beam, a first input electrode disposed on a first top portion of the first structural beam, and an output electrode. The apparatus further includes a first ferroelectric film disposed on a second top portion of the first input electrode, and a first resistive layer disposed on a third top portion of the first ferroelectric film, wherein a first electrode is positioned at a first end of the first resistive layer and a second electrode is positioned at a second end of the first resistive layer.

A configuration for a carbon nanotube (CNT) based memory device can include multiple CNT elements in order to increase memory cell yield by reducing the times when a memory cell gets stuck at a high state or a low state.

A configuration for a carbon nanotube (CNT) based memory device can include multiple CNT elements in order to increase memory cell yield by reducing the times when a memory cell gets stuck at a high state or a low state.

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.

A method of timing a resonant frequency of a nanoelectromechanical systems (NEMS) drum device is performed by applying a gate voltage between the drum membrane [100] and a back gate [104] to alter the resonant frequency of the membrane to a desired frequency; photoionizing the drum membrane with a laser to detune the membrane resonant frequency to a ground state frequency; and releasing the gate voltage to set the membrane to the desired resonant frequency. The method provides the basis for various applications including NEMS memory and photodetection techniques. The NEMS device may be implemented as a graphene/hBN membrane [100] suspended on a Si02 layer [102] deposited on a Si substrate [104].

A method of timing a resonant frequency of a nanoelectromechanical systems (NEMS) drum device is performed by applying a gate voltage between the drum membrane [100] and a back gate [104] to alter the resonant frequency of the membrane to a desired frequency; photoionizing the drum membrane with a laser to detune the membrane resonant frequency to a ground state frequency; and releasing the gate voltage to set the membrane to the desired resonant frequency. The method provides the basis for various applications including NEMS memory and photodetection techniques. The NEMS device may be implemented as a graphene/hBN membrane [100] suspended on a Si02 layer [102] deposited on a Si substrate [104].

The present invention relates to a mechanical interconnect memory, and more particularly, to a mechanical interconnect memory applicable to smart interconnect technology that reduces the power consumption of an interconnect layer.

A mechanical interconnect memory according to an embodiment of the present invention comprises: an upper electrode including: a spring part having at least one upward protruding portion between both ends of the spring part; and a moving part having one end of the moving part fixed to the at least one upward protruding portion of the spring part and the other end of the moving part being a free end of the moving part that is capable of moving up and down; and a lower electrode at least partially disposed under the moving part.

The present invention relates to a mechanical interconnect memory, and more particularly, to a mechanical interconnect memory applicable to smart interconnect technology that reduces the power consumption of an interconnect layer.

A mechanical interconnect memory according to an embodiment of the present invention comprises: an upper electrode including: a spring part having at least one upward protruding portion between both ends of the spring part; and a moving part having one end of the moving part fixed to the at least one upward protruding portion of the spring part and the other end of the moving part being a free end of the moving part that is capable of moving up and down; and a lower electrode at least partially disposed under the moving part.