The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.

The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be laminated and the laminated semiconductor apparatuses to be identified. A semiconductor apparatus that is laminated and integrated with a plurality of semiconductor apparatuses, includes a first penetrating electrode for connecting with the other semiconductor apparatuses and a second penetrating electrode that connects the first penetrating electrode and an internal device, the second penetrating electrode being arranged at a position that differs for each of the laminated semiconductor apparatuses. The second penetrating electrode indicates a lamination position at a time of lamination. An address of each of the laminated semiconductor apparatuses in a lamination direction is identified by writing using external signals after lamination. The present technology is applicable to a memory chip and an FPGA chip.

According to one embodiment, M (M represents an integer of 2 or larger) semiconductor chips and through electrodes for N (N represents an integer of 2 or larger) channels are provided. The M semiconductor chips are stacked in sequence. The through electrodes are embedded in the semiconductor chips to connect electrically the semiconductor chips in the direction of stacking. The connection destination of the through electrodes are exchanged between one or more upper and lower layers of the semiconductor chips.

A solid state drive (SSD) housing assembly includes an SSD housing and an extension frame. The SSD housing includes a first extension joint and a first mounting joint. The first mounting joint is a mechanism by which the housing can be mounted to an external device. The SSD housing has the form of a rectangular case in which an SSD module is held. The extension frame includes a second extension joint and a second mounting joint. The second mounting joint is a mechanism by which the frame can be mounted to the external device. The extension frame is attachable to and detachable from the SSD housing by virtue of the first extension joint and the second extension joint.

A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory. The memory includes a plurality of bits configured to electronically store data.

Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.

A semiconductor device includes an internal signal processing block suitable for generating an internal enable signal and an internal control signal that correspond to an external enable signal and an external control signal, and a monitoring unit suitable for outputting a monitoring signal that corresponds to a predetermined internal signal, based on the internal enable signal and the internal control signal, in an initial operation period.

A method for calibrating a current sensor which is configured to determine, in a vehicle's on-board power system, an electric operating current which flows through a measuring resistor, based on comparison of a voltage drop at the measuring resistor caused by the operating current and based on a rule which is dependent on the measuring resistor, including: determining an operating voltage drop brought about at the measuring resistor by the operating current; impressing a known electric calibration current into the measuring resistor, detecting an overall voltage drop brought about at the measuring resistor by the calibration current and the operating current, filtering the operating voltage drop from the overall voltage drop, such that a calibration voltage drop which is brought about by the calibration current remains, and calibrating the rule, dependent on the measuring resistor, based on the comparison of the calibration current and the calibration voltage drop.

A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source.

A semiconductor component includes a substrate including a plurality of source/drain implants in the form of rows and a charge storage structure disposed over the substrate. The charge storage structure includes at least three continuous layers including a first silicon oxide layer, a silicon nitride layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the silicon nitride layer. The semiconductor component further includes a plurality of gate structures in the form of columns disposed over the charge structure and extending perpendicular to the rows and further includes a radiation protection layer disposed over the charge storage structure and the plurality of gate structures. The radiation protection layer includes a radiation resistant material including boron having an isotope composition of at least 90% boron-11.