The invention relates to a method of manufacturing a device, the device comprising a superconducting zone (20) and an insulating zone (22) in an arrangement, comprising the steps of: depositing a buffer layer (12) on a portion of a substrate (10), etching the buffer layer (12) to obtain two zones (Z1, Z2), each first zone (Z1) being a zone in which the substrate (10) is covered by the buffer layer (12) and intended to form a respective superconducting zone (20), each second zone (Z2) being a zone in which the substrate (10) is exposed to form a respective insulating zone (22), and depositing a second layer (18) of superconducting material on the entire substrate portion (10), the first layer (12) being made of at least two superimposed sub-layers (14, 16).

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor layer is formed, a gate insulating layer is formed over the semiconductor layer, a metal oxide layer is formed over the gate insulating layer, and a gate electrode which overlaps with part of the semiconductor layer is formed over the metal oxide layer. Then, a first element is supplied through the metal oxide layer and the gate insulating layer to a region of the semiconductor layer that does not overlap with the gate electrode. Examples of the first element include phosphorus, boron, magnesium, aluminum, and silicon. The metal oxide layer may be processed after the first element is supplied to the semiconductor layer.

In various embodiments, controlled heating and/or cooling conditions are utilized during the fabrication of aluminum nitride single crystals and aluminum nitride bulk polycrystalline ceramics. Thermal treatments may also be utilized to control properties of aluminum nitride crystals after fabrication.

A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

A plasma processing apparatus includes: a first electrode on which a substrate is placed; a plasma generation source that generates plasma; a bias power supply that supplies bias power to the first electrode; a source power supply that supplies source power to the plasma generation source; and a controller. The controller performs a control such that a first state and a second state of the source power are alternately applied in synchronization with a high frequency cycle of the bias power, or a phase within one cycle of a reference electrical state indicating any one of a voltage, a current and an electromagnetic field measured in a power feed system of the bias power, and performs a control to turn OFF the source power at least at a negative side peak of the phase within one cycle of the reference electrical state.

A chip is mounted on a surface of the substrate, and the thermally conductive cover is disposed on a side that is of the chip and that is away from the substrate. There is a filling area on a surface that is of the thermally conductive cover and that faces the substrate, and the filling area is opposite to the chip. There is an accommodation cavity whose opening faces the substrate in the filling area. A thermal interface material layer is filled between the chip and a bottom surface of the accommodation cavity. Between an opening edge of the accommodation cavity and the substrate, there is a first gap connected to the accommodation cavity. The filling material encircles a side surface of the thermal interface material layer, so that the filling material separates the side surface of the thermal interface material layer from air.

A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.

The misalignment between light reception lenses and light reception elements in a lens integrated light reception element for converting a plurality of optical signals with different wavelengths into electric signals is easily inspected. The lens integrated light reception element includes one or more light reception lenses that receive the optical signals, one or more light reception elements each disposed on a main axis of the light reception lens and converting the optical signal into the electric signal, one or more inspection pinholes through which illumination light passes, and one or more inspection lenses each including a main axis parallel to the main axis of the light reception lens and converging the illumination light having passed through the inspection pinhole.

A semiconductor device includes: a pair of wire patterns configured to extend in a first direction and formed on a substrate to be spaced apart from each other in a second direction, the pair of wire patterns disposed closest to each other in the second direction; a gate electrode configured to extend in the second direction on the substrate, the gate electrode configured to surround the wire patterns; and first isolation layers configured to extend in the first direction between the substrate and the gate electrode and formed to be spaced apart from each other in the second direction, the first isolation layers overlapping the pair of wire patterns in a third direction perpendicular to the first and second directions.