A defect inspecting system includes a detector configured to image a sample and a host control device that acquires an inspection image including a defect and a plurality of reference images not including a defect site and generates a pseudo defect image by editing a predetermined reference image among the plurality of acquired reference images. An initial parameter is determined with which the pseudo defect site is detectable from the pseudo defect image. The host control device acquires a defect candidate site from the inspection image using the initial parameter, estimates a high-quality image from an image of a site corresponding to the defect candidate site using the parameter acquired in image quality enhancement, and specifies an actual defect site in the inspection image by executing defect discrimination. A parameter is determined with which a site close to the specified actual defect site is detectable using the inspection image.

A testing system for testing an image sensor, includes a probe card, a pogo block receiving output signals of the probe card, an interface board configured to receive output signals of the pogo block, convert the received output signals of the pogo block, and output the converted signals through a cable, and a testing apparatus connected to the interface board through the cable. The testing apparatus is configured to test the device under test through signals received through the cable. The interface board includes an active interface module configured to amplify the received output signals of the pogo block, convert the amplified signals into signals having a same frequency as the received output signals of the pogo block, and transmit the converted signals to the cable.

Systems, methods, and circuitries are provided for calibrating a heater used to heat an adjustable resistance network during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistance network including first resistance segments; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including second resistance segments thermally coupled to the first resistance segments; and interface circuitry coupled to the calibration resistor.

Disclosed is a method for producing a wafer map. More specifically, the present invention relates to: a method for producing a wafer map used for manufacturing chips in the semiconductor field, wherein a geographic information system (GIS) technique is used to produce the wafer map; and a method and system for providing wafer test results using same. According to an embodiment of the present invention, a semiconductor wafer is formed as a map by using the GIS technique, a coordinate system used in the GIS is utilized to create a map of the same size as an actual semiconductor wafer, and each of various constituent elements constituting the wafer can be stratified to reflect the actual size of the element to create a wafer map in which each of the elements is geocoded.

The invention provides a sample observation system including a scanning electron microscope and a calculator. The calculator: (1) acquires a plurality of images captured by the scanning electron microscope; (2) acquires, from the plurality of images, a learning defect image including a defect portion and a learning reference image not including the defect portion; (3) calculates estimation processing parameters by using the learning defect image and the learning reference image; (4) acquires an inspection defect image including a defect portion; and (5) estimates a pseudo reference image by using the estimation processing parameters and the inspection defect image.

Provided is a semiconductor element capable of inspecting a plurality of wires formed in parallel. A semiconductor element according to an embodiment includes: a first circuit (45B) connected to a first position of each of a plurality of wires of a first wire group (31) including the plurality of wires; a second circuit (45A) connected to a second position corresponding to an end of each of the plurality of wires; and a plurality of connection units (43) that connects a third circuit (14) with each of the plurality of wires, the plurality of connection units (43) being provided on a one-to-one basis to the plurality of wires between the first position and the second position of each of the plurality of wires.

This semiconductor wafer has formed therein a plurality of chips, each of which has incorporated therein a semiconductor element to be tested. The semiconductor wafer is characterized by comprising: first pads which are formed on the chips, and to which a plurality of probe needles are connected, the probe needles being connected to the semiconductor elements and used for testing the semiconductor elements; and a second pad that is used for performing a contact check on the probe needles, the second pad having a conductive section greater in length than the distance between the centers of the first pads.

A method of fabricating a four junction solar cell having an upper first solar subcell composed of a semiconductor material including aluminum and having a first band gap; a second solar subcell adjacent to said first solar subcell and composed of a semiconductor material having a second band gap smaller than the first band gap and being lattice matched with the upper first solar subcell; a third solar subcell adjacent to said second solar subcell and composed of a semiconductor material having a third band gap smaller than the second band gap and being lattice matched with the second solar subcell; and a fourth solar subcell adjacent to and lattice matched with said third solar subcell and composed of a semiconductor material having a fourth band gap smaller than the third band gap; wherein the fourth subcell has a direct bandgap of greater than 0.75 eV.

The purpose of the present invention is to provide a substrate inspection device that increases the flatness of a substrate during inspection, and improves the detection sensitivity of foreign matter. Therefore, the present invention is a substrate inspection device provided with a turntable on which a substrate to be inspected is mounted, and a clamp mechanism that holds the substrate on the turntable. The substrate inspection device is characterized in that the clamp mechanism has an abutting part that moves in an in-plane direction of the substrate and presses the substrate. Preferably, the abutting part contacts or separates from an outer peripheral side surface of the substrate by rotating centered on a rotational axis in an out-of-plane direction of the substrate.

A mount board has a plurality of terminals electrically connected to a plurality of pins of a semiconductor device, and a conductor pattern. An electrostatic withstand voltage test device includes a metal plate on which the mount board is installed, a power supply for applying a voltage to the metal plate, an insulator disposed between the metal plate and the mount board, a switch circuit connected between the terminals and ground wiring, and a controller for controlling the switch circuit. The switch circuit includes a plurality of first switches provided corresponding to the terminals and each connecting a corresponding terminal to the ground wiring. The controller turns on at least one first switch selected from the first switches when an electric charge stored in the conductor pattern is discharged to the ground wiring through the semiconductor device.