Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

An antenna structure according to an embodiment of the present disclosure includes a dielectric layer, and a plurality of antenna units arranged on a top surface of the dielectric layer. Each of the plurality of antenna units includes a radiator, a transmission line including a first transmission line and a second transmission line that extend in different directions to be connected to the radiator, an upper parasitic element adjacent to an upper portion of the radiator, and a lower parasitic element adjacent to a lower portion of the radiator and the transmission line. Feeding signals of different phases are applied to the first transmission line and the second transmission line.

A patch antenna device configured to receive a radio communication signal includes a circuit board, a patch antenna, and a parasitic element. The circuit board has a signal processing circuit placed thereon. The patch antenna is stacked on the circuit board and has a quadrangular radiation element. The parasitic element is disposed above the patch antenna so as to improve antenna gain characteristics of the patch antenna and configured such that the length of the upper side of the parasitic element is shorter than the width in a plan view of the radiation element of the patch antenna and that the length between the upper and lower sides of the parasitic element is longer than the length between the upper and lower sides of the radiation element of the patch antenna.

A semiconductor package includes a supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure; a frame on the supporting wiring structure, having a mounting space and a through hole, and including a conductive material; a semiconductor chip in the mounting space and electrically connected to the first redistribution conductive structure; a cover wiring structure on the frame and the semiconductor chip and including a second redistribution dielectric layer and a second redistribution conductive structure; an antenna structure on the cover wiring structure; a connection structure extending in the through hole and electrically connecting the first redistribution conductive structure to the second redistribution conductive structure; and a dielectric filling member between the connection structure in the through hole and the frame and surrounding the semiconductor chip, the frame, and the connection structure.

A sensor receiver may include a Rydberg cell configured to be exposed to a radio frequency (RF) signal having an RF data rate, and a probe source configured to generate a plurality of spaced apart pulsed probe beams within the Rydberg cell. Each pulse may have a temporal pulse width so that the RF data rate is greater than the reciprocal of the temporal pulse width. At least one excitation source may be coupled to the Rydberg cell. A detector may be positioned downstream from the Rydberg cell. The sensor receiver may be used in a RADAR system.

A sensor receiver may include a Rydberg cell configured to be exposed to a radio frequency (RF) signal having an RF data rate, and a probe source configured to generate a plurality of spaced apart pulsed probe beams within the Rydberg cell. Each pulse may have a temporal pulse width so that the RF data rate is greater than the reciprocal of the temporal pulse width. At least one excitation source may be coupled to the Rydberg cell. A detector may be positioned downstream from the Rydberg cell. The sensor receiver may be used in a RADAR system.

An antenna array includes: a plurality of patch antenna structures, wherein each patch antenna structure of the plurality of patch antenna structures includes: an active element configured to emit radiofrequency waves, a parasitic reflector element, and a parasitic director element, wherein the parasitic reflector element and the parasitic director element are configured to direct the radiofrequency waves emitted by the active element towards a corresponding emission direction; a first beamforming circuit configured to control the active elements of a first subset of patch antenna structures to provide beamforming in a first azimuth direction corresponding to the first subset of patch antenna structures, and a second beamforming circuit configured to control the active elements of a second subset of patch antenna structures to provide beamforming in a second azimuth direction corresponding to the second subset of patch antenna structures.

An electronic device may have an antenna embedded in a substrate. The substrate may have first layers, second layers on the first layers, and third layers on the second layers. The antenna may include a first patch on the first layers that radiates in a first band, a second patch on the second antenna layers that radiates in a second band, and a parasitic patch on the third layers. A short path may couple ground to a location on the first patch that allows the first patch to form a ground extension in the second band for the second patch without affecting performance of the first patch in the first band. The first layers may have a higher dielectric permittivity than the second and third layers to minimize the thickness of the substrate without requiring a separate dielectric loading layer over the substrate.

Global navigation satellite system (GNSS) radio frequency signals broadcast from geo-stationary satellites 20,000 km above the earth when received by GNSS receivers are fundamentally weak. Accordingly, these GNSS receivers are vulnerable to accidental and deliberate interference from a range of synthetic sources as well as natural sources. Existing anti jamming technologies such as controlled reception pattern antennas, adaptive antennas, null-steering antennas, and beamforming antennas etc. are expensive and incompatible with many lower cost and footprint limited applications. However, in many applications the GNSS antenna is mounted upon a fixed or mobile element such that accidental and intentional jammers tend to be in the plane of the antenna or below it. Accordingly, there are presented designs and techniques to improve the anti-jamming or interference performance of GNSS receivers by further reducing the responsivity of the GNSS receiver to signals in-plane or below the plane of the antenna.