A package apparatus comprises a first wiring layer, a first dielectric material layer, a first conductive pillar layer, a first buffer layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to the first surface. The first dielectric material layer is disposed within partial zone of the first wiring layer. The first conductive pillar layer is disposed on the second surface of the first wiring layer. The first buffer layer is disposed within partial zone of the first conductive pillar layer. The second wiring layer is disposed on the first buffer layer and one end of the first conductive pillar layer. The protection layer is disposed on the first buffer layer and the second wiring layer.

A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die includes a second substrate, and through-vias in the second substrate. A second die is over and bonded to the plurality of connectors. The first die and the second die are electrically coupled to each other through the redistribution lines. A second plurality of connectors is over the first die and the second die. The second plurality of connectors is electrically coupled to the first plurality of connectors through the through-vias in the second substrate.

This disclosure provides a package substrate and its fabrication method. The package substrate includes: a carrier; a first wiring layer formed on the carrier; a conductive pillar layer having a plurality of metal pillars on the first wiring layer; a molding compound layer formed on the first wiring layer, covering all the first wiring layer and the metal pillars, and exposing one end face of each metal pillar; a second wiring layer formed on the molding compound layer and the exposed end faces of the metal pillars; and a protection layer formed on the second wiring layer.

A wiring board includes a plurality of first terminal parts for electrically connecting with a control circuit and disposed corresponding to a plurality of first electrode parts, and first terminal wiring parts for electrically connecting the plurality of first electrode parts and the corresponding first terminal parts. Each of the first terminal wiring parts has, in at least a portion thereof falling in a circle with a radius of 10 mm centering around a boundary part between the first terminal wiring parts and the corresponding first terminal parts, a portion having a line width of 5 μm to 100 μm inclusive, the wiring resistance value of the first terminal wiring parts connected to the first terminal parts being 100 ohms to 10 kohms inclusive.

To provide an electronic component in which the bonding position and bonding strength of a lead terminal can be maintained even if re-heated, a crystal oscillator as an electronic component includes: a first substrate having a connection terminal; and a lead terminal having a connection pad connected to the connection terminal of the first substrate via an electrically conductive bonding member. The electrically conductive bonding member has a part overlapping with the connection terminal and the connection pad, and a part arranged on the outside of the connection pad, as viewed in a plan view. The connection pad is provided with a first area overlapping with the connection terminal and a second area extending from the first area. The second area is connected to the first substrate via an insulative bonding member.

In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.

Embodiments of the invention include an active mm-wave interconnect. In an embodiment, the active mm-wave interconnect includes a dielectric waveguide that is coupled to a first connector and a second connector. According to an embodiment, each of the first and second connectors may include a mm-wave engine. In an embodiment, the mm-wave engines may include a power management die, a modulator die, a demodulator die, a mm-wave transmitter die, and a mm-wave receiver die. Additional embodiments may include connectors that interface with predefined interfaces, such as small form-factor pluggables (SFP), quad small form-factor pluggables (QSFP), or octal small form-factor pluggables (OSFP). Accordingly, embodiments of the invention allow for plug and play functionality with existing servers and other high performance computing systems.

A semiconductor device having a semiconductor module that includes a first conductor layer and a second conductor layer facing each other, a group of semiconductor elements that are formed between the first and second conductor layers, and are connected to the second conductor layer respectively via a group of conductor blocks, and a circuit board having one end portion thereof located in a space between the semiconductor elements and the second conductor layer. Each semiconductor element includes first and second main electrodes respectively formed on first and second main surfaces thereof, and a control electrode that is formed on the second main surface. The first main electrode is electrically connected to the first conductor layer. The second main electrode is electrically connected to the second conductor layer via the respective conductor block. The circuit board includes a first wiring layer electrically connected to the control electrodes of the semiconductor elements.

A relay terminal block fixed to a fixing part by a screw includes a main body having a first surface facing the fixing part, and a second surface on a rear surface side of the first surface. The main body is formed with a recessed portion depressed from the second surface toward the first surface, a through-hole formed from a bottom surface of the recessed portion through to the first surface, and a protrusion that is provided at an edge of the recessed portion to protrude in a direction away from the second surface. The through-hole is formed to have an inner diameter larger than an outer diameter of a shaft of the screw and smaller than an outer diameter of a head of the screw, and the recessed portion is formed to have an inner diameter larger than the outer diameter of the head of the screw.

A power supply control apparatus includes: a control board that is configured to control a voltage of a battery module; and a bus bar module that is configured to electrically connect the control board to the battery module, the control board and the bus bar module are arranged in a stacked manner, and the bus bar module includes a plurality of bus bars that are made to be independent by cutting off junctions connecting the bus bars to each other and a resin member that supports the bas bars in a state where the junctions are exposed.