The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

Apparatus and methods for generating multiple oscillating signals. An example circuit generally includes a first voltage-controlled oscillator (VCO) circuit and a second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit. At least one of the first VCO circuit or the second VCO circuit generally includes: a pair of cross-coupled transistors comprising a first transistor and a second transistor, a first inductive element coupled between a first node and the drain of the first transistor, a second inductive element coupled between the first node and the drain of the second transistor, a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node, and a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node.

An oscillator circuit includes a first BAW oscillator, a first coupling stage, a second BAW oscillator, and a second coupling stage. The first BAW oscillator is configured to generate a first output signal at a frequency. The first coupling stage is coupled to the first BAW oscillator, and is configured to amplify the first output signal. The second BAW oscillator is coupled to the first coupling stage, and is configured to generate a second output signal at the frequency. The second output signal differs in phase from the first output signal. The second coupling stage is coupled to the first BAW oscillator and the second BAW oscillator, and is configured to amplify the second output signal and drive the first BAW oscillator.

The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.

An adiabatic resonator, an adiabatic oscillator, and an adiabatic oscillator system are disclosed. An adiabatic system is one that ideally transfers no heat outside of the system, thereby reducing the required operating power. The adiabatic resonator, which includes a plurality of tank circuits, acts as an energy reservoir, the missing aspect of previously attempted adiabatic computational systems. By using the adiabatic resonator as a feedback element with an amplifier, an adiabatic oscillator is formed. An adiabatic oscillator system is formed with a primary adiabatic oscillator feeding a plurality of secondary adiabatic oscillators. In this manner, the adiabatic oscillator system may be used to generate the multiple clock signals required of adiabatic computational logic elements, such as Split-level Charge Recovery Logic and 2-Level Adiabatic Logic. The adiabatic oscillator system stores enough energy to drive many individual adiabatic computational logic elements, permitting implementation of complex logic circuits.

An IQ generator capable of consuming lower power and occupying smaller die area. The IQ generator is configured without any synthesizer and divide-by-2 circuitry. The IQ generator may be configured to convert one or more phase outputs of a test tone generator (TTG) into I and Q signals. The IQ generator may receive as inputs differential outputs of a single phase of a TTG and/or multiple phase outputs of a TTG. The IQ generator may include one or more delay paths configured to generate the I and Q signals, and a calibration circuitry configured to compare the average pulse widths of the I and Q signals and provide one or more control signals to the one or more delay paths such that the I and Q signals are orthogonal in phase.

A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.

An adiabatic resonator, an adiabatic oscillator, and an adiabatic oscillator system are disclosed. An adiabatic system is one that ideally transfers no heat outside of the system, thereby reducing the required operating power. The adiabatic resonator, which includes a plurality of tank circuits, acts as an energy reservoir, the missing aspect of previously attempted adiabatic computational systems. By using the adiabatic resonator as a feedback element with an amplifier, an adiabatic oscillator is formed. An adiabatic oscillator system is formed with a primary adiabatic oscillator feeding a plurality of secondary adiabatic oscillators. In this manner, the adiabatic oscillator system may be used to generate the multiple clock signals required of adiabatic computational logic elements, such as Split-level Charge Recovery Logic and 2-Level Adiabatic Logic. The adiabatic oscillator system stores enough energy to drive many individual adiabatic computational logic elements, permitting implementation of complex logic circuits.

Apparatus and methods for rotary traveling wave oscillators (RTWOs) are disclosed. In certain embodiments, an RTWO system include an RTWO ring that carries a traveling wave, a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state, and a decoder system that controls selection of the plurality of selectable capacitors based on a frequency tuning code. The frequency tuning code includes a fine tuning code and a coarse tuning code, and the decoder system is operable to maintain a constant number of capacitors that toggle state for each value of the fine tuning code.

Apparatus and methods for rotary traveling wave oscillators (RTWOs) are disclosed. In certain embodiments, an RTWO system include an RTWO ring that carries a traveling wave, a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state, and a decoder system that controls selection of the plurality of selectable capacitors based on a frequency tuning code. The frequency tuning code includes a fine tuning code and a coarse tuning code, and the decoder system is operable to maintain a constant number of capacitors that toggle state for each value of the fine tuning code.