An method of determining a symbol according to a phase difference between input signals input in order of time may include calculating a first phase difference between a phase of a first previous signal received prior to a target signal and a phase of a second previous signal received prior to the first previous signal; calculating a second phase difference between a phase of the target signal and the phase of the second previous signal; calculating target likelihoods based on the first phase difference and the second phase difference; and determining an expected phase difference between the target signal and the first previous signal or an expected symbol for the target signal, based on the target likelihoods.

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

Systems and methods associated with phase frequency detection are disclosed. In one illustrative implementation, a phase frequency detection (PFD) circuit device may comprise first circuitry and second circuitry having a set input, a reset input, and an output, wherein the set input has a higher priority than the reset input, and additional circuitry arranged and operatively coupled to provide advantageous operation of the PFD circuit device. According to some implementations, for example, systems and methods with clock edge overriding reset features, extended detection range(s), and/or reduction of reverse charge after cycle slipping are provided.

Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

A phase angle can be measured between an analog signal and a reference signal by converting the analog signal to digital samples in a residue number system (RNS) analog-to-digital converter (ADC), based on a RNS scheme. The phase angle can be measured directly from the RNS values output by the RNS ADC, or the RNS values can be converted to a binary scheme, such as straight binary, offset binary or two's complement, before calculating the phase angle measurement.

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

The phase-synchronizing circuit according to the present disclosure includes: a signal source to output a signal; a signal separator to output part of the signal from the signal source as a transmission signal and receive a reflected signal of the transmission signal; a first phase controller to change a phase of the transmission signal from the signal separator according to a control signal; a signal reflector to pass the transmission signal from the first phase controller as an output signal and output part of the output signal as the reflected signal; and a phase comparator to receive part of the signal from the signal source as a reference signal, compare a phase of the reference signal with a phase of the reflected signal from the signal reflector, and output the control signal corresponding to a phase difference between the reference signal and the reflected signal to the first phase controller.

Technologies are provided for adaptive control of bias settings in a digital microphone. In some embodiments, a device includes a first component that provides data indicative of a clock frequency of operation in a functional mode of a digital microphone. The clock frequency clocks one or more microphone components having switching activity. The device also can include a second component that determines, using the clock frequency, an amount of bias current to supply to at least a first microphone component of the one or more microphone components. The device can further include a memory device that retains control parameters that include at least one of a first subset of parameters defining a relationship between current and frequency and a second subset of parameters defining a quantization of the relationship. The quantization including multiple bias current levels for respective frequency intervals.