A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.

A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.

A zero-insertion FIR filter architecture for filtering a signal with a target band and a secondary band. Digital filter circuitry includes an L-tap FIR (finite impulse response) filter, with a number L filter tap elements (L=0, 1, 2, . . . (L−1)), each with an assigned coefficient from a defined coefficient sequence. The L-tap FIR filter is configurable with a defined zero-insertion coefficient sequence of a repeating sub-sequence of a nonzero coefficient followed by one or more zero-inserted coefficients, with a number Nj of nonzero coefficients, and a number Nk of zero-inserted coefficients, so that L=Nj+Nk. The L-tap FIR filter is configurable as an M-tap FIR filter with a nonzero coefficient sequence in which each of the L filter tap elements is assigned a non-zero coefficient, the M-tap FIR filter having an effective length of M=(Nj+Nk) non-zero coefficients.

A zero-insertion FIR filter architecture for filtering a signal with a target band and a secondary band. Digital filter circuitry includes an L-tap FIR (finite impulse response) filter, with a number L filter tap elements (L=0, 1, 2, . . . (L−1)), each with an assigned coefficient from a defined coefficient sequence. The L-tap FIR filter is configurable with a defined zero-insertion coefficient sequence of a repeating sub-sequence of a nonzero coefficient followed by one or more zero-inserted coefficients, with a number Nj of nonzero coefficients, and a number Nk of zero-inserted coefficients, so that L=Nj+Nk. The L-tap FIR filter is configurable as an M-tap FIR filter with a nonzero coefficient sequence in which each of the L filter tap elements is assigned a non-zero coefficient, the M-tap FIR filter having an effective length of M=(Nj+Nk) non-zero coefficients.

A digital-to-analog converter is provided. The digital-to-analog converter comprises a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter comprises a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells comprise a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells comprise different numbers of inverter cells. The digital-to-analog converter additionally comprises an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

An adaptive analog parallel combiner circuit for receiver data recovery from a communication signal is provided. The circuit includes a summer that sums outputs of a plurality of filter taps in parallel, including zeroth and first through Nth filter taps, each filter tap having as input the communication signal or a version thereof, wherein N is a finite integer greater than or equal to two. The zeroth filter tap has an amplifier with gain controlled by a zeroth adaptive gain control coefficient, and each of the first through Nth filter taps having an all pass filter and gain controlled amplification, with gain controlled by a corresponding one of a first through Nth adaptive gain control coefficients and the all pass filter implementing a transfer function having a zero and a pole equaling each other and at a base frequency divided by a corresponding integer from one through N.

According to an example, discrete-time analog filtering may include receiving an input signal, and sampling the input signal to determine sampled input signal values related to the input signal.

According to an example, discrete-time analog filtering may include receiving an input signal, and sampling the input signal to determine sampled input signal values related to the input signal.

A reconfigurable discrete time analog signal processor includes a finite impulse response (FIR) filter configured to receive a portion of an RF transmit signal, to receive FIR coefficients, and to generate a leakage cancellation signal based on the portion of the RF transmit signal and the FIR coefficients, the FIR filter including sample and hold (SH) circuits configured to receive the portion of the RF transmit signal, to sample the portion of the RF transmit signal at successive sample times according to a sample clock, and to generate sampled analog voltage signals, and analog multipliers coupled to the SH circuits and configured to multiply the sampled analog voltage signals by binary multiplication factors to generate the leakage cancellation signal.

The exemplary embodiments provide a parallel implementation of filters with recursive transfer functions. This can enable a filter to act as a frame filter that may process a frame of multiple samples of data in parallel rather than being limited to processing a single sample of data at a time. Each frame contains plural input samples of data values. The input samples are from a common source and have a time dependency. The exemplary embodiments are suitable for implementing various types of filters in parallel, such as cascaded integrator comb filters, biquad filters and other types of infinite impulse response (IIR) filters. The exemplary embodiments may use polyphase decomposition to decompose a filter with a recursive transfer function into multiple polyphase component filters. The polyphase component filters may be applied to respective samples of data in a parallel pipelined configuration to produce filtered output for the samples of data in parallel.