A modulation device includes: a signal splitter configured to generate: i) an M-bit wide partial signal comprising M more significant bits of an N-bit wide input signal; and ii) an L-bit wide partial signal comprising L less significant bits of the N-bit wide input signal, where L=N−M; a first modulation unit configured to generate a 1-bit wide pulse density modulation signal on the basis of the L-bit wide partial signal; a summation unit configured to generate an M-bit wide summation signal on the basis of the M-bit wide partial signal and the 1-bit wide pulse density modulation signal; and a second modulation unit configured to generate a 1-bit wide pulse width modulation signal on the basis of the M-bit wide summation signal.

Phased array systems rely on the production of an exact carrier frequency to function. Reconstructing digital signals by specified amplitude and phase is accomplished explicitly by inducing frequency shifts away from a base frequency implied by phase changes. Shifting the carrier frequency of a digitally controlled phased array while preserving the timing of the individual phase pulses enables more efficient driving of the phased array system when the phase of the drive signals change dynamically in time.

Phased array systems rely on the production of an exact carrier frequency to function. Reconstructing digital signals by specified amplitude and phase is accomplished explicitly by inducing frequency shifts away from a base frequency implied by phase changes. Shifting the carrier frequency of a digitally controlled phased array while preserving the timing of the individual phase pulses enables more efficient driving of the phased array system when the phase of the drive signals change dynamically in time.

The present technology relates to a signal processing apparatus, a signal processing method, and a program that permit switching between a plurality of DSD signals having different sampling frequencies using a simple configuration. An acquisition section acquires a digital audio signal having a given sampling frequency selected from among the plurality of digital audio signals acquired by delta-sigma modulating an audio signal at a plurality of sampling frequencies. An interpolation section subjects the acquired digital audio signal to a pre-interpolation process when the sampling frequency of the acquired digital audio signal is lower than an operating clock of a delta-sigma demodulator. The present technology is applicable, for example, to a signal processing apparatus.

A satellite communication system processes a plurality of input signals to generate beamformed signals, drives a plurality of nonlinear power amplifiers with the beamformed input signals to produce RF signals for transmission; and transmits the RF signals with a plurality of Tx antenna elements. Conversion to and from linear signals to and from nonlinear or digitized signals is performed. Temporal or spatial decorrelation of the beamformed signals is employed to reduce the impact of intermodulation products. In some cases the power amplifiers are nonlinear, and can be one-sided or two-sided and produce two or three distinct output levels.

Phased array systems rely on the production of an exact carrier frequency to function. Reconstructing digital signals by specified amplitude and phase is accomplished explicitly by inducing frequency shifts away from a base frequency implied by phase changes. Shifting the carrier frequency of a digitally controlled phased array while preserving the timing of the individual phase pulses enables more efficient driving of the phased array system when the phase of the drive signals change dynamically in time.

A modulation device includes: a signal splitter configured to generate: i) an M-bit wide partial signal comprising M more significant bits of an N-bit wide input signal; and ii) an L-bit wide partial signal comprising L less significant bits of the N-bit wide input signal, where L=NM; a first modulation unit configured to generate a 1-bit wide pulse density modulation signal on the basis of the L-bit wide partial signal; a summation unit configured to generate an M-bit wide summation signal on the basis of the M-bit wide partial signal and the 1-bit wide pulse density modulation signal; and a second modulation unit configured to generate a 1-bit wide pulse width modulation signal on the basis of the M-bit wide summation signal.

The present technology relates to a signal processing apparatus, a signal processing method, and a program that permit switching between a plurality of DSD signals having different sampling frequencies using a simple configuration.

An acquisition section acquires a digital audio signal having a given sampling frequency selected from among the plurality of digital audio signals acquired by delta-sigma modulating an audio signal at a plurality of sampling frequencies. An interpolation section subjects the acquired digital audio signal to a pre-interpolation process when the sampling frequency of the acquired digital audio signal is lower than an operating clock of a delta-sigma demodulator. The present technology is applicable, for example, to a signal processing apparatus.

A distributed antenna system includes a master unit including a downlink RF input operable to receive an RF input signal from a downlink port of a base station, a first optical port, and a second optical port. The distributed antenna system also includes a first remote unit coupled to the first optical port. The first remote unit comprises a downlink antenna port and a first uplink antenna port and a second remote unit coupled to the second optical port of the master unit. The second remote unit comprises a downlink antenna port and a second uplink antenna port. The master unit is operable to transmit a first RF signal associated with the first RF uplink signal to a first uplink port of the base station and transmit a second RF signal associated with the second RF uplink signal to a second uplink port of the base station.

A communication verification system is provided. The communication verification system includes a local transmitting-end unit, a remote receiving-end unit, and a repeater device. The local transmitting-end unit is set to a first computing mode and outputs an initial value. The remote receiving-end unit is set to a second computing mode. The repeater device receives the initial value from the local transmitting-end unit and outputs an initial value to the remote receiving-end unit according to the second computing mode. The repeater device receives and stores a computation result from the remote receiving-end unit, and then outputs a confirmation signal to the local transmitting-end unit according to the first computing mode. The repeater device outputs the computation result to the local transmitting-end unit for verification when the repeater device receives a query signal from the local transmitting-end unit.