A chip, a self-calibration circuit and method for chip parameter offset upon power-up are disclosed. The circuit includes a counting circuit, a calibration data latch circuit, a calibration data selection circuit and a parameter calibration circuit. The counting circuit outputs a sequentially scanned counting signal when receiving a valid enabling signal. The calibration data latch circuit latches the counting signal when receiving a valid latch signal. The calibration data selection circuit selects the counting signal latched by the calibration data latch circuit as a calibration signal when receiving the valid latch signal, otherwise selects the counting signal currently outputted as the calibration signal. The parameter calibration circuit implements a parameter calibration based on the calibration signal in a calibration mode, while outputs the valid latch signal when the parameter calibration satisfies a preset requirement. Thus, a parameter calibration with a higher accuracy and flexibility is realized in a cheaper way.

Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.

A low power SRAM (static RAM) for an image sensor includes a voltage generation circuit for providing a positive supply voltage V.sub.P and a negative supply V.sub.N, wherein VDD>V.sub.p>V.sub.n>V.sub.gnd; a plurality of memory cells coupled to a respective plurality of column sense lines in a pixel array, the plurality of memory cells receiving differential inputs dp and dn; and a Gray counter coupled to switchably couple V.sub.P and V.sub.N to the differential inputs dp and dn of the plurality of memory cells. A method of operating an image sensor with a low power SRAM includes acquiring an image by the image sensor; generating V.sub.P and V.sub.N such that V.sub.DD>V.sub.P>V.sub.N>V.sub.gnd; receiving an output g of a column of pixels at a clock input of a memory cell; and switchably coupling V.sub.P and V.sub.N to the differential inputs dp and dn of a plurality of memory cells in the SRAM according to a codeword from a Gray counter.

An image sensor includes a pixel sensor that senses an incident light and outputs a sampling signal of an analog shape, a sampler that compares the sampling signal and a ramp signal and outputs a comparison signal being time-axis length information, and a gray counter that counts a length of the comparison signal in synchronization with a clock signal and outputs a digital value. The gray counter includes a first flip-flop that divides the clock signal by 2 and generates a first gray code signal, a second flip-flop that delays a first data signal being a four-divided signal of the clock signal and outputs a second gray code signal, and a third flip-flop that delays the second gray code signal being two-divided and outputs a third gray code signal.

A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.

A counting device, including multiple counting circuit stages and a first logic operation circuit, is provided. The counting circuit stages are serially coupled in sequence. A first counting circuit stage performs a counting action according to a first clock signal and generates a first counting result. Second to Nth counting circuit stages perform counting actions according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit provides the first counting result to be the second clock signal according to an indication signal.

Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.