A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.

A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.

A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.

A semiconductor integrated circuit includes a harmonic oscillator circuit, a first switch circuit configured to cause an oscillating state of the harmonic oscillator circuit to switch between an on state and an off state, a detector circuit configured to produce a voltage responsive to an amplitude of the oscillating output of the harmonic oscillator circuit, a decision circuit configured to detect whether the voltage produced by the detector circuit exceeds a threshold in synchronization with a clock signal, and a second switch circuit configured to control whether or not to apply noise from a noise source to the harmonic oscillator circuit.