In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.

A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

A method is provided for performing zero-copy distribution of data samples between applications running on the same node in a system using an Object Management Group (OMG) Data Distribution Service (DDS) and/or a Real-Time Publish Subscribe (RTPS) protocol. Further provided is a method for selecting the network representation to communicate with a DataReader in a system using an Object Management Group (OMG) Real-Time Publish Subscribe (RTPS) protocol. Still further provided is the combination of these two methods to communicate transparently using zero-copy within the same node and not using zero-copy for different nodes. Embodiments of this invention lead to a relatively small communication latency that is constant and independent of the data size for applications running within a single node.

A method is provided for performing zero-copy distribution of data samples between applications running on the same node in a system using an Object Management Group (OMG) Data Distribution Service (DDS) and/or a Real-Time Publish Subscribe (RTPS) protocol. Further provided is a method for selecting the network representation to communicate with a DataReader in a system using an Object Management Group (OMG) Real-Time Publish Subscribe (RTPS) protocol. Still further provided is the combination of these two methods to communicate transparently using zero-copy within the same node and not using zero-copy for different nodes. Embodiments of this invention lead to a relatively small communication latency that is constant and independent of the data size for applications running within a single node.

A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.