In one embodiment, a system to deterministically transfer partitions of contiguous computer readable data in constant time includes a computer readable memory and a modulo address generator. The computer readable memory is organized into D banks, to contain contiguous data including a plurality of data elements of size M which are constituent data elements of a vector with N data elements, the data elements to start at an offset address O. The modulo address generator is to generate the addresses of the data elements of a vector with i data elements stored in the computer readable memory, the modulo address generator including at least one forward permutaton to permute data elements with addresses of the form O+M*i where 0<=i<N. Other embodiments are described and claimed.

Neural network specific hardware acceleration optimizations are disclosed, including an optimized multicast network and an optimized DRAM transfer unit to perform in constant or linear time. The multicast network is a set of switch nodes organized into layers and configured to operate as a Bene{hacek over (s)} network. Configuration data may be accessed by all switch nodes in the network. Each layer is configured to perform a Bene{hacek over (s)} network transformation of the -previous layer within a computer instruction. Since the computer instructions are pipelined, the entire network of switch nodes may be configured in constant or linear time. Similarly a DRAM transfer unit configured to access memory in strides organizes memory into banks indexed by prime or relatively prime number amounts. The index value is selected as not to cause memory address collisions. Upon receiving a memory specification, the DRAM transfer unit may calculate out strides thereby accessing an entire tile of a tensor in constant or linear time.

A machine can be accessed and controlled with the help of an interface device. The customizable interface device contains device elements that define features relating to the external representation and internal functionality of the interface device, as linked to one or more machines. An operator can use a configuration station to implement single or reoccurring queries that interact with the interface device and corresponding machines. In particular, the queries target the configuration of device elements in the interface device. The process can include temporarily unloading unused features from active memory and mirroring property changes initialized by a source. An emulator can assist in the configuration process by providing a preliminary software representation of the interface device hardware. A user can develop, test, and reconfigure functions on the emulator before loading the finalized platform to the interface device.

A machine can be accessed and controlled with the help of an interface device. The customizable interface device contains device elements that define features relating to the external representation and internal functionality of the interface device, as linked to one or more machines. An operator can use a configuration station to implement single or reoccurring queries that interact with the interface device and corresponding machines. In particular, the queries target the configuration of device elements in the interface device. The process can include temporarily unloading unused features from active memory and mirroring property changes initialized by a source. An emulator can assist in the configuration process by providing a preliminary software representation of the interface device hardware. A user can develop, test, and reconfigure functions on the emulator before loading the finalized platform to the interface device.

In one embodiment, a system to deterministically transfer partitions of contiguous computer readable data in constant time includes a computer readable memory and a modulo address generator. The computer readable memory is organized into D banks, to contain contiguous data including a plurality of data elements of size M which are constituent data elements of a vector with N data elements, the data elements to start at an offset address O. The modulo address generator is to generate the addresses of the data elements of a vector with i data elements stored in the computer readable memory, the modulo address generator including at least one forward permutaton to permute data elements with addresses of the form O+M*i where 0<=i<N. Other embodiments are described and claimed

Surreptitious communication with a user is disclosed by way of binary tactile inputs and outputs. A communication module of a computing device receives a first alphanumeric message that is converted to a first binary coded message that is rendered as first and second vibration outputs that are humanly distinguishable. A touch input component of one of a touch screen and a motion sensor detects a sequential pattern of user touches. Distinguished first and second tactile inputs in the sequential pattern identify a second binary coded message that is converted into a second alphanumeric message. First and second alphanumeric messages are comprised of a combination of characters selected from one or more of: (i) letters; (ii) numerals; and (iii) symbols.

A digital full-bandwidth direct-forwarding racon system and a working method adopt a direct forwarding architecture, which combines a digital broadband DRFM real-time forwarding technology and an encoding response architecture with dots replacing a line. A transmitting antenna and a receiving antenna operate independently and simultaneously, and directly and indiscriminately encode and forward all of the radar query signals in an operating frequency band, thus preserving complete waveform information while realizing a Morse encoding of the response information. The digital full bandwidth direct forwarding racon system is equivalent to a target with a special target characteristic, where when a radar signal within the operating frequency band irradiates the target, an echo signal with a specified Morse encoding modulation characteristic would be generated.

A digital full-bandwidth direct-forwarding racon system and a working method adopt a direct forwarding architecture, which combines a digital broadband DRFM real-time forwarding technology and an encoding response architecture with dots replacing a line. A transmitting antenna and a receiving antenna operate independently and simultaneously, and directly and indiscriminately encode and forward all of the radar query signals in an operating frequency band, thus preserving complete waveform information while realizing a Morse encoding of the response information. The digital full bandwidth direct forwarding racon system is equivalent to a target with a special target characteristic, where when a radar signal within the operating frequency band irradiates the target, an echo signal with a specified Morse encoding modulation characteristic would be generated.

Neural network specific hardware acceleration optimizations are disclosed, including an optimized multicast network and an optimized DRAM transfer unit to perform in constant or linear time. The multicast network is a set of switch nodes organized into layers and configured to operate as a Beneš network. Configuration data may be accessed by all switch nodes in the network. Each layer is configured to perform a Beneš network transformation of the -previous layer within a computer instruction. Since the computer instructions are pipelined, the entire network of switch nodes may be configured in constant or linear time. Similarly a DRAM transfer unit configured to access memory in strides organizes memory into banks indexed by prime or relatively prime number amounts. The index value is selected as not to cause memory address collisions. Upon receiving a memory specification, the DRAM transfer unit may calculate out strides thereby accessing an entire tile of a tensor in constant or linear time.

A method for estimating, by a device using an FDR scheme, a non-linear self-interference signal channel comprises a step of estimating a non-linear self-interference signal channel using a first sequence set included in a predefined first sequence set, wherein the predefined first sequence set is defined in consideration of non-linear self-interference signal components in an RF transmission chain and an RF reception chain of the device.