The invention comprises a method of forming a magnetic free layer having a (100) texture and a novel magnetic pinning structure having a (100) textured or cube-textured reference layer through a non-epitaxial texturing approach so that an excellent coherent tunneling effect is achieved in a pMTJ element due to its texture structure of Fe or CoFe BCC (100)/MgO rocksalt (100)/Fe or CoFe BCC (100). The invention also discloses a pMTJ element comprising a soft-magnetic adjacent layer having at least one high-permeability material layer having a near-zero magnetostriction. Correspondingly, a high MR ratio and a coherent domain reversal of the magnetic free layer can be achieved for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.

A memory device is provided, the memory device comprising a contact pillar in a dielectric layer. A magnetic tunnel junction may be provided over the contact pillar. A barrier layer may be provided on a sidewall of the magnetic tunnel junction and extending over a horizontal surface of the dielectric layer. A spacer may be provided over the barrier layer.

A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.

A memory slot including a pad formed of a stack of regions made of thin layers, including a first region made of a nonmagnetic conducting material; a second region made of a magnetic material exhibiting a magnetization in a direction perpendicular to the principal plane of the pad; a third region made of a nonmagnetic conducting material of different characteristics to those of the first region; the pad resting on a conducting track adapted to cause the flow of a programming current of chosen sense, in which the pad has an asymmetric shape with respect to any plane perpendicular to the plane of the layers and parallel to the central axis of the track, and with respect to its barycenter.

According to various embodiments, there is provided a memory device including at least one sense amplifier having a first side and a second side, wherein the second side opposes the first side; a first array including a plurality of memory cells arranged at the first side; a second array including a plurality of memory cells arranged at the second side; a first row including a plurality of mid-point reference units arranged at the first side; and a second row including a plurality of mid-point reference units arranged at the second side, wherein each mid-point reference unit of the first row is configured to generate a first reference voltage, and wherein each mid-point reference unit of the second row is configured to generate a second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the first array based on the second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the second array based on the first reference voltage.

The present invention relates to a sensor device which has high S/N and excellent temperature characteristics. A sensor device has a semiconductor substrate, a first metal wiring layer provided on the semiconductor substrate, a first insulating layer provided on the first metal wiring layer, a compound semiconductor sensor element provided on the first insulating layer, a second metal wiring layer provided on the compound semiconductor sensor element and the first insulating layer, and a second insulating layer provided on the second metal wiring layer. A third insulating layer is provided between the first metal wiring layer and the second metal wiring layer, and the compound semiconductor sensor element is provided in the third insulating layer.

An MTJ structure having vertical magnetic anisotropy is provided. The MTJ structure having vertical magnetic anisotropy can comprise: a substrate; an artificial antiferromagnetic layer located on the substrate; a buffer layer located on the artificial antiferromagnetic layer, and including W or an alloy containing W; a first ferromagnetic layer located on the buffer layer, and having vertical magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer, and having vertical magnetic anisotropy. Accordingly, in the application of bonding the artificial antiferromagnetic layer with a CoFeB/MgO/CoFeB structure, the MTJ structure having improved thermal stability at high temperature can be provided by using the buffer layer therebetween.

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.