A semiconductor device according to an embodiment has a circuit board having a first surface facing a first side, and a second surface facing a second side on a side opposite to the first side. The semiconductor device has a chip mounted on the first surface. The semiconductor device has a heat transfer member joined to the second surface with a first joint layer therebetween. The semiconductor device has a heat dissipation member joined to a surface of the heat transfer member facing the second side with a second joint layer therebetween. Each of the first joint layer and the second joint layer is a sintered body.

A semiconductor package includes: a molded body having opposite first and second sides; at least one semiconductor die encapsulated by the molded body; and a die carrier having opposite first and second sides. The semiconductor die is arranged over the first side of the die carrier. The second side of the die carrier is at least partially exposed from the second side of the molded body, forming at least one exposed portion of the die carrier. The first side of the molded body includes a first portion protruding from a second portion in a vertical direction perpendicular to the first side, forming a planar surface. The second portion extends completely along at least one edge of the first side. A center point of the first portion is in vertical alignment with a center point of the exposed portion.

Methods, systems, and devices for die side interconnect are described. A semiconductor assembly may include a stack of first dies (e.g., memory dies) coupled with a second die (e.g., a logic die) using a sideways architecture. For example, the semiconductor assembly may include multiple first dies, where a top surface of one the first dies is coupled with a bottom surface of another of the first dies to form the stack. The first dies each have a side surface coupled with an upper surface of the second die. The first dies each include a conductive via extending from the top surface of the respective first die at least partially towards the bottom surface of the respective first die. The first dies each include a redistribution layer coupled with the conductive via and extending parallel with the top surface of the respective first die.

Methods, systems, and devices for die side interconnect are described. A semiconductor assembly may include a stack of first dies (e.g., memory dies) coupled with a second die (e.g., a logic die) using a sideways architecture. For example, the semiconductor assembly may include multiple first dies, where a top surface of one the first dies is coupled with a bottom surface of another of the first dies to form the stack. The first dies each have a side surface coupled with an upper surface of the second die. The first dies each include a conductive via extending from the top surface of the respective first die at least partially towards the bottom surface of the respective first die. The first dies each include a redistribution layer coupled with the conductive via and extending parallel with the top surface of the respective first die.

The semiconductor device of the embodiment includes a first plate portion and a second plate portion. The semiconductor device includes a top electrode including a first surface, a second surface, and a plurality of first electrode pillars provided on the second surface side. The semiconductor device includes a bottom electrode including a third surface, a fourth surface, and a plurality of second electrode pillars provided on the third surface side. The semiconductor device includes a plurality of first semiconductor chips located between the first electrode pillars and the second electrode pillars, and electrically connected to the first electrode pillars and the second electrode pillars. The semiconductor device includes at least one first recess provided on the first surface and a width of the at least one first recess in a second direction perpendicular to the first direction being larger than a width of the first electrode pillars.

The semiconductor device of the embodiment includes a first plate portion and a second plate portion. The semiconductor device includes a top electrode including a first surface, a second surface, and a plurality of first electrode pillars provided on the second surface side. The semiconductor device includes a bottom electrode including a third surface, a fourth surface, and a plurality of second electrode pillars provided on the third surface side. The semiconductor device includes a plurality of first semiconductor chips located between the first electrode pillars and the second electrode pillars, and electrically connected to the first electrode pillars and the second electrode pillars. The semiconductor device includes at least one first recess provided on the first surface and a width of the at least one first recess in a second direction perpendicular to the first direction being larger than a width of the first electrode pillars.

A semiconductor package includes: a plurality of leads including first leads and second leads; a first substrate connected to the first leads; a second substrate connected to one or more connector elements; and an encapsulant covering the first substrate, the second substrate and inner portions of the first leads and the second leads.

A semiconductor package includes: a plurality of leads including first leads and second leads; a first substrate connected to the first leads; a second substrate connected to one or more connector elements; and an encapsulant covering the first substrate, the second substrate and inner portions of the first leads and the second leads.