A nitride semiconductor device includes a SiC substrate having a hexagonal crystal structure and including a main surface inclined with respect to a c-plane at an off-angle from 2 to 6 in a specific crystal direction, a nitride semiconductor layer located on the main surface of the SiC substrate and including an electron transit layer and an electron supply layer, and a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer. The main surface is parallel to a first direction, a second direction orthogonal to the first direction, and a third direction coinciding with the specific crystal direction in plan view. The source electrode and the drain electrode are separated in the first direction. The gate electrode extends in the second direction between the source electrode and the drain electrode. The first direction intersects the third direction at an angle of 9015.

Integrated circuit structures having backside source or drain contact differentiated access are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.

An integrated circuit device includes a first semiconductor layer, a second semiconductor layer, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a first contact plug. The second semiconductor layer is above the first semiconductor layer. The first and second semiconductor layers are vertically spaced apart from each other. The first source/drain epitaxial structure is on a side of the first semiconductor layer. The second source/drain epitaxial structure is on a side of the second semiconductor layer and above the first source/drain epitaxial structure. The first source/drain epitaxial structure has a portion extending beyond a sidewall of the second source/drain epitaxial structure from a top view. The first contact plug is over a frontside of the first source/drain epitaxial structure. The first contact plug overlaps the portion of the first source/drain epitaxial structure from the top view.

A semiconductor IC device includes a conductive through device connection. The connection may be located within a double diffusion break (DDB) region that separates active regions. The connection may include a faux S/D region between a frontside contact and a backside contact. The semiconductor IC device may further include a first and/or second diffusion break isolation rail. The connection may be between the first and second diffusion break isolation rails. The connection location within the DDB region may resultantly increase packing densities of the semiconductor IC device. Further, the connection may reduce routing complexities and resistance through the semiconductor IC device, which may improve semiconductor IC device performance. Further, the connection may utilize mirrored structure instances (e.g., frontside contact, backside contact, faux S/D region, or the like) as that are used by microdevices (e.g., transistors, or the like) within the active regions, which may decrease fabrication complexities.

Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is off (Vg approximately 0 volts). When the transistor is on (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.

According to one embodiment, a display device comprises a flexible substrate, a first insulating film disposed on the flexible substrate, a switching element disposed on the first insulating film, a signal wiring electrically connected with the switching element, a first organic film disposed on the signal wiring, a connection wiring disposed on the first organic film, a second organic film disposed on the connection wiring and a pad electrode disposed on the second organic film. The connection wiring is located between the first organic film and the second organic film and is in contact with the first organic film and the second organic film.

Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A semiconductor structure includes a semiconductor substrate, a first isolation dam, a plurality of switching transistors and a second isolation dam. The semiconductor substrate includes a trench, an isolation region formed by a region where the trench is located, a plurality of active regions defined by the isolation region, and an electrical isolation layer, the electrical isolation layer being located on one side, away from an opening of the trench, of the trench; the first isolation dam fills the trench; the switching transistor is at least partially embedded in the active region of the semiconductor substrate; and the second isolation dam is at least partially located between the first isolation dam and the electrical isolation layer.