The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

A silicon photonic chip, a LiDAR, and a mobile device are disclosed. The silicon photonic chip includes a cladding, a transceiving waveguide module, a first photoelectric detection module, and a first polarization rotator. An emitting waveguide of the transceiving waveguide module extends along a first direction and is configured to transmit and emit a detection light, and the first receiving waveguide of the transceiving waveguide module is arranged at intervals along a second direction from the emitting waveguide and is configured to receive and transmit an echo light. The first photoelectric detection module is configured to receive a first local oscillator light and the echo light output by the first receiving waveguide. The first polarization rotator is disposed upstream of the first photoelectric detection module.

A method of manufacturing a transistor structure includes forming a plurality of trenches in a substrate, lining the plurality of trenches with a dielectric material, forming first and second substrate regions at opposite sides of the plurality of trenches, and filling the plurality of trenches with a conductive material. The plurality of trenches includes first and second trenches aligned between the first and second substrate regions, and filling the plurality of trenches with the conductive material includes the conductive material extending continuously between the first and second trenches.

A method of manufacturing a transistor structure includes forming a plurality of trenches in a substrate, lining the plurality of trenches with a dielectric material, forming first and second substrate regions at opposite sides of the plurality of trenches, and filling the plurality of trenches with a conductive material. The plurality of trenches includes first and second trenches aligned between the first and second substrate regions, and filling the plurality of trenches with the conductive material includes the conductive material extending continuously between the first and second trenches.

An A/D conversion circuit includes a reference voltage source to generate a calibration voltage, a multiplexer to receive an analog signal and the calibration voltage, and output the analog signal selected in a normal mode and the calibration voltage selected in a calibration mode or a self-diagnosis mode, an A/D converter to convert an output signal from the multiplexer into a digital signal, a non-volatile memory to hold the digital signal and calibration data, a digital calibration part to calibrate the digital signal in case of inputting the analog signal to the A/D converter in the normal mode based on the calibration data, and a self-diagnosis circuit to diagnose the A/D converter based on the digital signal in case of inputting the calibration voltage to the A/D converter in the self-diagnosis mode, and the digital signal stored in the non-volatile memory.

A display substrate comprises a base substrate and a first metal layer, a second metal layer, a first electrode pattern, a second electrode pattern, a first insulating layer and a second insulating layer formed above the base substrate. The first insulating layer is located over the first metal layer, the second insulating layer is located above the first insulating layer, the first electrode pattern and the second metal layer are located between the first insulating layer and the second insulating layer; a via hole is arranged at a position directly above the first metal layer to which the first insulating layer and the second insulating layer correspond, one end of the first electrode pattern is connected with the second metal layer, the other end extends into the via hole, the second electrode pattern is in the via hole and connected with the first electrode pattern and the first metal layer.

An integrated circuit (IC) comprises a first conductor in one layer of the IC, a second conductor in another layer of the IC, and a first metal plug connecting the first and second conductors. The IC further comprises an atomic source conductor (ASC) in the one layer of the IC and joined to the first conductor, and a second metal plug connecting the ASC to a voltage source of the IC. The first conductor and the ASC are configured to be biased to different voltages so as to establish an electron path from the second metal plug to the first metal plug such that the ASC acts as an active atomic source for the first conductor.

A semiconductor device in which a variation of transistor characteristics is small is provided. The semiconductor device includes a transistor. The transistor includes a first insulator, a first oxide over the first insulator, a first conductor, a second conductor, and a second oxide, which is positioned between the first conductor and the second conductor, over the first oxide, a second insulator over the second oxide, and a third conductor over the second insulator. A top surface of the first oxide in a region overlapping with the third conductor is at a lower position than a position of a top surface of the first oxide in a region overlapping with the first conductor. The first oxide in the region overlapping with the third conductor has a curved surface between a side surface and the top surface of the first oxide, and the curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.

A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first layout structure, the second layout structure, or both the first and second layout structures. A dimension of the rectangular-shaped interlevel connection layout structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection layout structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second layout structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines.

Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.