According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

A radio frequency device includes an optically transparent, electrically insulating substrate; a plurality of optically transparent, electrically conductive cells disposed on the substrate; a thin film transistor electrically coupled between an optically transparent electrode of a first one of the cells and an optically transparent electrode of a second one of the cells; and an optically transparent conductive control trace electrically coupled to a control terminal of the transistor. In an example, at least one of the cells is a transparent conductive oxide thin film. Electrodes of the transistor may also be optically transparent.

A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

A method of forming a semiconductor device comprises the following steps. A dielectric layer is formed over a substrate. A 2D material layer is formed over the dielectric layer. An adhesion layer is formed over the 2D material layer. Source/drain electrodes are formed on opposite sides of the adhesion layer. A first high-k gate dielectric layer is formed over the adhesion layer, wherein the adhesion layer has a material different from a material of the first high-k gate dielectric layer.

Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.

A semiconductor device includes a substrate, a buffer layer on the substrate, an n type epitaxial layer extending upward from the buffer layer in one direction, and having a fin channel, a p type layer disposed on the buffer layer and surrounding the side and upper surfaces of the n type epitaxial layer, a gate insulating layer on the p type layer, and a gate electrode on the gate insulating layer.

Related to the field of display panels, an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes: the base substrate, the buffer layer, the active layer, the gate insulation layer, the gate, the interlayer insulation layer, the source, and the drain, which are stacked together. By using the gate insulation layer as a conductive mask of the active layer, and by adjusting the width of the gate and the width of the gate insulation layer, a width difference between the channel region and the gate is within the preset range, which reduces the problem of excessive width difference caused by the diffusion phenomenon of the channel region, and can at the same time meet the switching characteristics requirements of the thin film transistor and the definition requirements of the display panel.

Lateral gallium oxide transistor includes a gallium oxide substrate, an n-type gallium oxide epitaxial layer epitaxially grown on the gallium oxide substrate, an insulating layer defining a gate region, a source region, and a drain region on the n-type gallium oxide epitaxial layer, a diffusion barrier layer deposited on the n-type gallium oxide epitaxial layer exposed in the gate region, a p-type nickel oxide layer deposited on the diffusion barrier layer, a dielectric layer deposited on the p-type nickel oxide layer, a gate electrode layer deposited on the dielectric layer, and a source electrode and a drain electrode formed on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region.

A semiconductor device includes an oxide semiconductor layer, a first electrode and a second electrode, which are arranged apart from each other on the oxide semiconductor layer, a metal oxide layer arranged between the oxide semiconductor layer and at least one of the first electrode and the second electrode, and a metal nitride layer arranged between the metal oxide layer and the oxide semiconductor layer.