A method and a device for preparing an inductance element, an inductance element, and a superconducting circuit are provided. The method includes acquiring a compound for preparing an inductance element, a superconducting coherence length and a magnetic field penetration depth of the compound meeting a preset condition; and annealing the compound to cause decomposition between a non-superconductor phase and a superconductor phase in the compound to generate the inductance element, the kinetic inductance of the inductance element being greater than the geometric inductance of the inductance element.

A method and a device for preparing an inductance element, an inductance element, and a superconducting circuit are provided. The method includes acquiring a compound for preparing an inductance element, a superconducting coherence length and a magnetic field penetration depth of the compound meeting a preset condition; and annealing the compound to cause decomposition between a non-superconductor phase and a superconductor phase in the compound to generate the inductance element, the kinetic inductance of the inductance element being greater than the geometric inductance of the inductance element.

A cryo-compatible quantum computing arrangement includes a microelectronic quantum computing component having a substrate structure, a plurality of first contact elements and a plurality of conductive feedthroughs through the substrate structure, wherein the conductive feedthroughs are electrically connected on a first main surface area of the substrate structure to associated first contact elements of the microelectronic quantum computing component, and a further microelectronic component having a plurality of second contact elements, wherein on a second main surface area of the substrate structure, the conductive feedthroughs are electrically connected to associated second contact elements of the further microelectronic component, and wherein the conductive feedthroughs each include, between the first and second contact elements, a layer element including a first material that is superconducting at a quantum computing operating temperature, and a filling element including a second material that is electrically conductive.

According to one embodiment, a coupler includes first to fourth capacitors, first and second inductors, and a first Josephson junction. The first capacitor includes a first capacitor end portion and a first capacitor other-end portion. The first inductor includes a first inductor end portion, and a first inductor other-end portion. The second inductor includes a second inductor end portion, and a second inductor other-end portion. The first Josephson junction includes a first Josephson junction end portion, and a first Josephson junction other-end portion. A space is surrounded with the first inductor, the second inductor, and the first Josephson junction. The third capacitor includes a third capacitor end portion, and a third capacitor other-end portion. The fourth capacitor includes a fourth capacitor end portion, and a fourth capacitor other-end portion.

A semiconductor-ferromagnetic insulator-superconductor hybrid device comprises a semiconductor component, a ferromagnetic insulator component, and a superconductor component. The semiconductor component has at least three facets. The ferromagnetic insulator component is arranged on a first facet and a second facet. The superconductor component is arranged on a third facet and extends over the ferromagnetic insulator component on at least the second facet. The device is useful for generating Majorana zero modes, which are useful for quantum computing. Also provided are a method of fabricating the device, and a method of inducing topological behaviour in the device.

A quantum device capable of preventing contacts from being displaced is provided. A quantum device includes a quantum element in which a quantum circuit is provided, a socket including contacts and a housing, the contacts being in contact with a terminal of the quantum element, and the housing supporting the contacts, and a board including a board substrate. At least one of the housing and the board substrate includes a hole, another one of the housing and the board substrate includes a fixing part disposed inside the hole and a body part other than the fixing part, and the fixing part and the body part are integrally formed.

Provided is a three-dimensional (3D) transmon qubit apparatus including a body portion, a driver, a transmon element disposed in an internal space of the body portion, a first tunable cavity module disposed in the internal space of the body, and comprising a first superconductive metal panel; and a second tunable cavity module disposed in the internal space of the body, and comprising a second superconductive metal panel, wherein the transmon element is disposed between the first superconductive metal panel and the second superconductive metal panel; wherein the first tunable cavity module and the second tunable cavity module are configured to adjust a distance between the first superconductive metal panel and the second superconductive metal panel, and wherein the driver is configured to tune a resonance frequency by adjusting a 3D cavity by adjusting the distance between the first superconductive metal panel and the second superconductive metal panel.

A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.