Provided are an SiC-semiconductor device (1) having properties capable of maximizing the device strength when cut from an SiC-semiconductor wafer (11) by SnB, and a method of manufacturing the SiC-semiconductor device.

The SiC-semiconductor device is produced by, after forming scribe lines (L) in the wafer (11) with a scribing tool, dividing the wafer with external-force application along the lines (L). Created in a sidewall surface of the device (1) is a longitudinal stripe (TL) extending continuously to C surface from a predetermined depth in the sidewall surface exclusive of plastically-deformable region of Si surface and vertical-cracking region formed immediately below the plastically deformable region. The stripe (TL) fulfills the condition of being rectilinearly-shaped or the condition where exterior angle formed by intersection of a longitudinal stripe (TL) extending upward from the C (lower) surface with a deflected stripe (KL) resulting from first-time deflection of the stripe (TL) falls within 10.

Provided herein is a method for producing a die attach adhesive film sheet, comprising: Providing a first release substrate layer, a die attach adhesive layer, and a dicing tape layer, and joining the first release substrate layer, the die attach adhesive layer, and the dicing tape layer in that order to form a multi-layer structure; Working the multi-layer structure to form a circular preformed die attach adhesive film sheet, wherein during said working the first release substrate receives a z-directional indentation therein; and Removing the first release substrate with the z-directional indentation therein from the die attach adhesive layer, and placing in its stead a second release substrate in contact with the die attach adhesive layer.

A method of manufacturing a semiconductor element includes: a first process that includes forming a first modified portion in the substrate, and forming a second modified portion at a position next to the first modified portion in a first direction, and a process of forming a plurality of third modified portions arranged in a thickness direction of the substrate at positions that are closer to the first face of the substrate than is the first modified portion and overlapping the first modified portion in a plan view. No modified portions are formed at positions that are next to the third modified portions in the first direction to overlap the second modified portions in a plan view. The number of the first modified portions arranged in the thickness direction is equal to or less than the number of the third modified portions arranged in the thickness direction.

In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

A method of manufacturing semiconductor chips having a side wall sealing is described. The method includes forming dicing trenches in a semiconductor wafer. The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches. Semiconductor chips are separated from the semiconductor wafer.

In one example, an electronic device includes an electronic component including a first side, a second side opposite to the first side, a lateral side connecting the first side to the second side, bond pads adjacent to the first side, and a passivation layer over the first side and including openings exposing the bond pads. A redistribution structure is over the passivation layer and the bond pads. The redistribution structure includes a conductive structure coupled to the bond pads and a dielectric structure. The conductive structure includes outward terminals. External interconnects are coupled to the outward terminals and a protection layer covers the lateral side of the electronic component. Other examples and related methods are also disclosed herein.

A wafer processing method including applying a laser beam to the wafer along projected dicing lines of the wafer while focusing the laser beam within the wafer, thereby forming modified layers in the wafer along the projected dicing lines, after the modified layers have been formed in the wafer, affixing a first tape to a reverse side of the wafer, after the first tape has been affixed to the reverse side of the wafer, developing cracks initiated from the modified layers in the wafer to divide the wafer into a plurality of device chips, and expanding the first tape to form gaps between the device chips, and after the gaps have been formed between the device chips, inserting a cutting blade into the gaps and causing the cutting blade to cut into side faces of the device chips, thereby cutting off the side faces of the device chips.

The disclosure provides a method of manufacturing an electronic device. The method of manufacturing the electronic device includes the following steps: providing a transparent carrier having an accommodation space, wherein the transparent carrier has a first mark; disposing a sample in the accommodation space of the transparent carrier, wherein the sample has a second mark; calculating an offset of the sample according to the first mark, the second mark, and a standard value; and forming a third mark on the sample or the transparent carrier according to the offset. The method of manufacturing of the electronic device of the disclosure may improve process yield or reliability.

A method of manufacturing a semiconductor element includes preparing integrated circuit chips, obtaining warpage information of each of the integrated circuit chips, deforming at least a portion of a chip stress control pattern of each of the integrated circuit chips according to the warpage information of each of the integrated circuit chips, laminating the integrated circuit chips on a carrier substrate with adhesive layers interposed therebetween, curing the adhesive layers, and removing chip scribe lane areas from the integrated circuit chips.

Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.