A workpiece cutting method includes: a first step of pasting an expandable sheet on a workpiece; a second step of irradiating, after the first step, the workpiece with laser light to form a modified region and expanding the expandable sheet to divide the workpiece into a plurality of chips, and meanwhile, to form a gap disposed between the plurality of chips and extending to a side surface of the workpiece; a third step of irradiating the expandable sheet with an ultraviolet light after the first step; a fourth step of filling, after the second step and the third step, the gap with resin from an outer edge part of the workpiece including the side surface; a fifth step of curing the resin after the fourth step; and a sixth step of taking out the chips from above the expandable sheet after the fifth step.

A wafer processing method includes forming a start point of division along division lines, providing, on a front surface of the wafer, a protective member for protecting the front surface of the wafer, grinding a back surface of the wafer to a desired thickness, forming division grooves in the division lines to divide the wafer into individual device chips, providing an expandable sheet to the back surface of the wafer and removing the protective member from the front surface of the wafer, coating the front surface of the wafer with an adhesive liquid having flowability, expanding and shrinking the sheet so as to allow the adhesive liquid to enter each of the division grooves and to discharge the adhesive liquid from the division grooves, and removing the adhesive liquid from the front surface of the wafer to clean a side surface of each of the division grooves.

Provided is a wafer processing method including a back surface film processing step of removing or roughening a back surface film that is applied to the back surface of the wafer, a protective member providing step of providing a protective member to a front surface of the wafer before or after the back surface film processing step is carried out, and a back surface grinding step of holding the protective member side on a chuck table and grinding the back surface of the wafer with grinding stones to thin the back surface of the wafer to a desired thickness.

A method for forming semiconductor devices from a semiconductor wafer includes cutting a first surface of a semiconductor wafer to form a first region that extends partially through the semiconductor wafer and the first region has a bottom portion. The method further includes directing a beam of laser light to the semiconductor wafer such that the beam of laser light is focused within the semiconductor wafer between the first surface and the second surface thereof and the beam of laser light further cuts the semiconductor wafer by material ablation to form a second region aligned with the first region. A resulting semiconductor device is disclosed as well.

A substrate for semiconductor fabrication having an interior portion bound by a perimeter, wherein all of the perimeter has been selectively treated to form a hardened perimeter having an increased hardness relative to the interior portion is disclosed herein. Methods to selectively treat a substrate for semiconductor fabrication are also disclosed.

An electronic package and a manufacturing method thereof are provided. The electronic package includes an electronic component and a shielding layer. The electronic component has an active surface, an inactive surface opposite to the active surface, and a side surface connecting the active surface and the active surface. The shielding layer is disposed on the electronic component and directly contacts and completely covers the inactive surface and the side surface. The shielding layer is formed directly on the surface of the electronic component, thereby shielding electromagnetic interference, reducing the size of the electronic package, and lowering production costs.

A semiconductor package includes a redistribution structure including redistribution patterns, first and second chip structures on the redistribution structure and electrically connected to the redistribution patterns, a first mold covering at least a portion of each of the first and second chip structures, an interconnection chip including interconnection patterns electrically connected to the redistribution patterns and a plurality of insulating layers having third surfaces in which respective ones of the interconnection patterns are embedded, through-vias electrically connected to the redistribution patterns, a second mold covering at least a portion of each of the through-vias and the interconnection chip. Each third surface includes a first region, and a second region between the first region and an upper surface of the respective interconnection pattern embedded in the third surface. The second region defines a step between the first region and the upper surface of the interconnection pattern embedded in the third surface.

A chip manufacturing method includes: preparing a wafer unit having a protective member fixed to one surface of a wafer and having a recess and a loop-shaped protrusion surrounding the recess on the other surface side of the wafer, the protective member including a first sheet in contact with the wafer, a resin layer stacked on the first sheet, and a second sheet stacked on the resin layer; processing the wafer and the protective member along a boundary between the recess and the loop-shaped protrusion to separate the recess and the loop-shaped protrusion from each other; and after separating of the recess and the loop-shaped protrusion, holding the protective member side of the wafer on a holding table and dividing the wafer from the other surface side to manufacture a plurality of chips.

A stealth dicing process for singulating semiconductor dies from a wafer substrate and associated systems and methods are disclosed herein. In some embodiments, the process includes forming a first cleavage line in a wafer that extends generally in a first direction and defines a first surface corresponding to a sidewall of a semiconductor die. The process can also include forming a second cleavage line in the wafer that extends generally in a second direction perpendicular and defines a second surface oriented generally perpendicular to the first surface. Further, the second surface can correspond to at least a portion of a top surface or at least a portion of a bottom surface of the semiconductor die. In some embodiments, the process forms the second cleavage line for a first semiconductor die at a different depth from the second cleavage line for a second semiconductor die.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.