A method of manufacturing a semiconductor package includes disposing a substrate strip having a plurality of semiconductor chips in a bottom mold, the bottom mold including sets of injection holes arranged on one side of the substrate strip, coupling the bottom mold and a top mold to contact each other, the top mold including cavities open toward corresponding ones of the sets of injection holes, individually injecting a first molding material and a second molding material into each of the cavities through injection holes included in a corresponding one of the sets of injection holes, respectively, forming a molding compound including the first molding material and the second molding material in the cavities, separating the top mold and the bottom mold from each other, curing the molding compound covering the semiconductor chips to form a mold structure, and cutting the mold structure.

A slurry containing: abrasive grains; a compound X; and water, in which the abrasive grains contain cerium oxide, and a hydrogen bond term dH in Hansen solubility parameters of the compound X is 15.0 MPa.sup.1/2 or more. A polishing method including polishing a surface to be polished by using this slurry.

The invention discloses a semiconductor chip, which includes: a transistor region; and a crack-stop ring structure, which is arranged around the transistor region, wherein the crack-stop ring structure includes a peripheral crack-stop structure surrounding the transistor region along four sides of the semiconductor chip. The corner crack-stop structure is provided only at the corner of the semiconductor chip. The corresponding angles of the corner crack-stop structure and the peripheral crack-stop structure are both right angles. The corner crack-stop structure and the peripheral crack-stop structure are connected to each other in a non-perpendicular manner, thereby forming a closed area at the chip corner.

A method for manufacturing a semiconductor device includes a step of preparing a semiconductor substrate that has a first main surface on one side and a second main surface on the other side, the semiconductor substrate on which a plurality of device forming regions and an intended cutting line that demarcates the plurality of device forming regions are set, a step of forming a first electrode that covers the first main surface in each of the device forming regions, a step of forming a second electrode that covers the second main surface, a step of partially removing the second electrode along the intended cutting line such that the semiconductor substrate is exposed, and forming a removed portion that extends along the intended cutting line, and a step of cutting the semiconductor substrate along the removed portion.

A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700 C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.

A power semiconductor device includes a substrate including SiC of a first conductivity type and including a first region and a second region, a drift layer of the first conductivity type on the substrate and in the first and second regions, a well region of a second conductivity type on the drift layer and in in the first region, a source region of the first conductivity type within the well region, a gate electrode on and extending along an upper surface of the well region, a source electrode connected to the source region in the first region, a metal layer connected to the drift layer in the second region, and a passivation layer covering the source electrode and the metal layer. The passivation layer defines a recessed portion between the first region and the second region.

A method of processing a composite structure including a thin layer of single-crystal silicon carbide disposed on a polycrystalline silicon carbide carrier substrate, includes, after formation of electronic component elements on a front face of the composite structure, grinding a rear face of the composite structure and removing a work-hardened layer present on the surface of the rear face as a result of the grinding process.

A method of processing a composite structure including a thin layer of single-crystal silicon carbide disposed on a polycrystalline silicon carbide carrier substrate, includes, after formation of electronic component elements on a front face of the composite structure, grinding a rear face of the composite structure and removing a work-hardened layer present on the surface of the rear face as a result of the grinding process.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.