Patent classifications
H10P95/00
Industrial magazine rack
Provided is an industrial magazine rack in which a biasing mechanism for biasing a stopper member to a closed position or an open position is prevented from coming into contact with a board-shaped member housed in a rack main body. The industrial magazine rack includes a base fixed to a lower surface of a top plate or an upper surface of a bottom plate, a pivot bracket for supporting the stopper member, which is supported by the base so as to be pivotable on a pivot axis extending in a vertical direction on an outside of a side plate, and a torsion coil spring having a first end portion mounted to the base on an outside of a pivot center of the pivot bracket in a left and right direction and a second end portion mounted to the pivot bracket between the pivot center of the pivot bracket and the first end portion in the left and right direction, and the torsion coil spring is formed to bias the stopper member toward the closed position when the second end portion is on one side of an imaginary line connecting the pivot center of the pivot bracket and the first end portion, and bias the stopper member toward the open position when the second end portion is on another side of the imaginary line.
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over first and second fin structures, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a first source/drain (S/D) epitaxial structure formed adjacent to the gate structure in the first fin structure. The S/D epitaxial structure comprises first and second S/D epitaxial layers. The semiconductor structure may include a second S/D epitaxial structure formed adjacent to the gate structure in the second fin structure. A contact structure may be formed over the first and second S/D epitaxial structures.
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM
Provided is an information processing apparatus including an acquisition unit that acquires sensor data including a plurality of sensor values measured by a substrate processing apparatus and attribute information that affects a temporal change in the substrate processing apparatus, a classification unit that classifies the sensor data based on the attribute information, and a display unit that displays a plot corresponding to the sensor data in a different mode for each classification, on a correlation graph between the plurality of sensor values.
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM
An information processing apparatus includes: an acquisition unit that acquires sensor data including a first sensor value and a second sensor value measured in a substrate processing apparatus when the substrate processing apparatus is not executing a process; and a display unit that displays information representing a correlation between the first sensor value and the second sensor value.
PALLADIUM COBALT OXIDE THIN FILM, DELAFOSSITE-TYPE OXIDE THIN FILM, SCHOTTKY ELECTRODE HAVING DELAFOSSITE-TYPE OXIDE THIN FILM, METHOD FOR PRODUCING PALLADIUM COBALT OXIDE THIN FILM, AND METHOD FOR PRODUCING DELAFOSSITE-TYPE OXIDE THIN FILM
A palladium cobalt oxide thin film, a delafossite-type oxide thin film, a Schottky electrode having a delafossite-type oxide thin film, a method for producing a palladium cobalt oxide thin film, and a method for producing a delafossite-type oxide thin film are provided. In the palladium cobalt oxide thin film, the crystal grain size in the film is 100 nm or more and 500 nm or less, the thickness is greater than the critical film thickness, and the roughness value in the thickness direction is 4 nm or less.
HIGHLY INTEGRATED ENVIRONMENTAL SENSOR
A system and method for a highly integrated environmental sensor and process for manufacturing said sensor is disclosed. Examples of the present disclosure may include an integrated sensor. The integrated sensor may include a redistribution layer (RDL). The integrated sensor may also include a control circuit coupled to the RDL. The integrated sensor may additionally include an analog front-end circuit coupled to the RDL and the control circuit. The integrated sensor may further include an environmental sensor coupled to the analog front-end circuit. The environmental sensor may include a first sensing element deposited in a first trench etched on the RDL using inkjet material deposition.
TRANSISTOR AND METHOD FOR FABRICATING TRANSISTOR
A transistor having a minute size is provided. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer is provided over the first conductive layer and includes an opening reaching the first conductive layer and a depressed portion surrounding the opening in a plan view. The second conductive layer is provided to cover the inner wall of the depressed portion and includes a region facing the semiconductor layer with the first insulating layer therebetween. The semiconductor layer is provided to include a region overlapping with the opening and is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer. The second insulating layer is provided in contact with the top surface of the semiconductor layer. The third conductive layer is provided over the second insulating layer to cover the inner wall of the opening and includes a region facing the semiconductor layer with the second insulating layer therebetween.
Bonding apparatus, bonding system, and bonding method
A bonding apparatus includes a first holder, a second holder, a moving unit, a housing, an interferometer, a first gas supply and a second gas supply. The first holder is configured to attract and hold a first substrate. The second holder is configured to attract and hold a second substrate. The moving unit is configured to move a first one of the first holder and the second holder in a horizontal direction with respect to a second one thereof. The interferometer is configured to radiate light to the first one or an object moved along with the first one to measure a horizontal distance thereto. The first gas supply is configured to supply a clean first gas to an inside of the housing. The second gas supply is configured to supply a second gas to a space between the interferometer and the first one or the object.
Bonding apparatus, bonding system, bonding method, and recording medium
A bonding apparatus configured to bond substrates includes a first holder configured to vacuum-exhaust a first substrate to attract and hold the first substrate on a bottom surface thereof; a second holder disposed under the first holder, and configured to vacuum-exhaust a second substrate to attract and hold the second substrate on a top surface thereof; a mover configured to move the first holder and the second holder relatively in a horizontal direction; a laser interferometer system configured to measure a position of the first holder or the second holder which is moved by the mover; a linear scale configured to measure a position of the mover; and a controller configured to control the mover based on a measurement result of the laser interferometer system and a measurement result of the liner scale.
Planarization method
A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.