A semiconductor structure includes a contact plug on a source/drain region of a transistor, and a via on the contact plug. The via includes a lower portion and an upper portion over the lower portion, the lower portion of the via tapers upward, and the upper portion of the via tapers downward. The semiconductor structure further includes a metal line on the via.

A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.

A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

A semiconductor device and a manufacturing method therefor are disclosed, in which a first opening is formed in a first metal layer by etching away part of the first metal layer, and a second metal layer is filled in the first opening and is electrically connected to the remainder of the first metal layer. A TSV extends sequentially through a substrate and a partial thickness of a dielectric layer so that the second metal layer is exposed therein, and an interconnect layer in the TSV is electrically connected to the second metal layer. In this way, the first metal layer can be picked up as long as projections of the second metal layer and the interconnect layer on the substrate are encompassed within a projection of the first metal layer on the substrate, without any additional lateral area of the first metal layer being occupied by the TSV.

Disclosed are a method and a device for repairing a circuit on an array substrate, and an array substrate. The method includes: determining a section to be repaired on each signal line; applying a conductive material to form a repair line between two ends of the section to be repaired, the repair line being connected with two ends of the section to be repaired; and applying an insulating material to form a cover layer above the repair line, the cover layer completely covers the surface of the repair line.

A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.

Provided is a conductive structure and a method for forming such a structure. The method includes forming a treatable layer by depositing a layer comprising a metal over a structure; performing a directional treatment process on a targeted portion of the treatable layer to convert the targeted portion to a material different from a non-targeted portion of the treatable layer, wherein the directional treatment process is selected from the group consisting of nitridation, oxidation, chlorination, carbonization; and selectively removing the non-targeted portion from the structure, wherein the targeted portion remains over the structure.

A method includes obtaining a base structure including a stack of dielectric layers disposed on a substrate. The stack of dielectric layers includes a first photosensitive dielectric layer including a first photosensitive dielectric material sensitive to a first radiation dose, a second photosensitive dielectric layer including a second photosensitive dielectric material sensitive to a second radiation dose different from the first radiation dose, and a barrier layer disposed between the first photosensitive dielectric layer and the second photosensitive dielectric layer. The method further includes forming a dual damascene structure from the base structure using a dual damascene process.

A device comprises a non-insulator structure, a dielectric layer, a metal via, a metal line, and a dielectric structure. The dielectric layer is over the non-insulator structure. The metal via is in a lower portion of the dielectric layer. The metal line is in an upper portion of the dielectric layer. The dielectric structure is embedded in a recessed region in the lower portion of the dielectric layer. The dielectric structure has a tapered top portion interfacing the metal via.