A structure includes an Sn layer or an Sn alloy layer formed above a substrate, and an under barrier metal formed between the substrate and the Sn layer or Sn alloy layer. The under barrier metal is an Ni alloy layer containing Ni, and at least one selected from W, Ir, Pt, Au, and Bi, and can sufficiently inhibit generation of an intermetallic compound through a reaction, caused due to metal diffusion of a metal contained in the substrate, between the metal and Sn contained in the Sn layer or Sn alloy layer.

A method includes forming a plurality of dielectric layers, forming a lower portion of a seal ring including a plurality of metal layers, each extending into one of the plurality of dielectric layers, depositing a first passivation layer over the plurality of dielectric layers, forming an opening in the first passivation layer, forming a via ring in the opening and physically contacting the lower portion of the seal ring, and forming a metal ring over the first passivation layer and joined to the via ring. The via ring and the metal ring form an upper portion of the seal ring. The metal ring includes an edge portion having a zigzag pattern. The method further includes forming a second passivation layer on the metal ring, and performing a singulation process to form a device die, with the seal ring being proximate edges of the device die.

A chip package structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a chip, a molding layer and a package cover. The conductive substrate has first and second board surfaces opposite to each other, and a die-bonding region is defined on the first board surface. The chip is disposed on the first board and located in the die-bonding region, and is electrically connected to the conductive substrate. The molding layer is disposed on the first board surface and surrounds the die-bonding region and the chip. The package cover is disposed on the molding layer, and the package cover, the molding layer and the conductive substrate jointly define an enclosed space surrounding the chip. Two of the conductive substrate, the molding layer and the package cover are connected to each other through a mortise-tenon joint structure.

A semiconductor module comprises a metallic sheet comprising a first surface. The semiconductor module further comprises a semiconductor die coupled to the first surface of the metallic sheet. An electrically insulative housing comprises a circumferential frame, wherein the electrically insulative housing encloses the semiconductor die and at least a part of the first surface of the metallic sheet. Furthermore, a joining section of the circumferential frame is directly joined to the first surface of the metallic sheet, wherein an electrically inducible element is enclosed near the joining section of the circumferential frame.

A flip-chip bonding-based antenna packaging structure and its manufacturing method are provided. The flip-chip bonding-based antenna packaging structure includes a lead frame structure and a redistribution structure disposed above the lead frame structure. The redistribution structure includes a first surface and a second surface. The lead frame structure is disposed on the redistribution structure and includes a metal member, a first active element, and a passive element. The metal member includes a base portion, a first supporting portion on the base portion, and an extension portion adjacent to the first supporting portion. The extension portion extends from the base portion, and the first supporting portion is parallel to the extension portion. The first active element is disposed between the first supporting portion and the first surface. The passive element is disposed on the second surface and is electrically connected to the first active element.

A mask-to-donor alignment method for laser-induced forward transfer includes (a) directing a laser beam onto a mask to produce a masked beam including one or more separate sub-beams, each sub-beam being transmitted by a respective aperture of the mask, (b) viewing each sub-beam, as transmitted by a donor substrate carrying one or more devices, to obtain imagery indicating in each sub-beam a shadow of a corresponding one of the one or more devices, and (c) based on the imagery, adjusting position of the masked beam and the donor substrate, relative to each other, so as to align each device with respect to the corresponding sub-beam. This in-situ observation of the relative alignment between the donor substrate and the masked beam produces an improved alignment accuracy, as compared to the indirect fiducial-based alignment method. Alignment accuracies better than 0.2 m, and associated sub-1 m LIFT positioning accuracies, have been demonstrated.

A substrate mounting method, performed by a mounting apparatus includes providing a stack including a substrate, a first protective member, and a second protective member, the first protective member being an outermost layer, cutting the stack to obtain at least one chip, removing the first protective member from the at least one chip, heating at least a portion of the second protective member, holding the at least one chip by attaching a bonding head of the mounting apparatus to the heated second protective member, and bonding the at least one chip to a base substrate using the bonding head.

A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.

This semiconductor device manufacturing device comprises: a stage; a bonding head; a copying mechanism provided on the bonding head; and a controller that executes the copying process to adjust a facing surface to be parallel to a reference plane by having the facing surface, which is a holding surface or a chip end face, follow the reference plane 110, which is a planar surface of the stage or a substrate. In the copying process, the controller moves the bonding head relative to the surface direction of the reference plane with the facing surface left abutting the reference plane in a state with the copying mechanism switched to a free state, until the axial direction position of the bonding head reaches a stipulated reference position, and when the axial direction position reaches the reference position, switches the copying mechanism to a locked state.

A semiconductor device according to one aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and extends in a direction forming an angle of 30 to 30 with respect to the first direction. A semiconductor device according to another aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and has a joint portion that is long in one direction in plan view and an angle of a long direction of the joint portion with respect to the first direction is 30 to 30.