C23C14/0682

APPARATUS FOR MANUFACTURING DISPLAY DEVICE, METHOD OF MANUFACTURING MASK ASSEMBLY, AND METHOD OF MANUFACTURING DISPLAY DEVICE
20240060169 · 2024-02-22 ·

An apparatus for manufacturing a display device includes a mask assembly, the mask assembly including a silicon substrate having a first surface, a second surface opposite the first surface, and a first opening portion penetrating the first surface and the second surface, and a support substrate on the second surface, the support substrate having a second opening portion connected to the first opening portion. The first opening portion at the first surface is less in width than the first opening portion at the second surface.

Silanized ITO electrode with ITO nanoparticles for aqueous sulfide detection

A silanized ITO electrode modified with ITO nanoparticles is described. ITO nanoparticles of cubic and semispherical shapes are immobilized on a silanized ITO film. The electrode may be used in an electrolytic cell to detect aqueous sulfide with a 0.5-1.4 M limit of detection. The electrode shows high specificity towards aqueous sulfide and a high reproducibility in measurement.

PROCESS INTEGRATION METHOD TO TUNE RESISTIVITY OF NICKEL SILICIDE
20190371610 · 2019-12-05 ·

Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a Ni.sub.xSi.sub.1-x layer on the substrate, where x is between about 0.01 and about 0.99.

Method of forming nickel silicide materials
11965236 · 2024-04-23 · ·

Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15? C. to about 27? C., annealing the first nickel silicide seed layer at a temperature of 400? C. or less such as over 350? C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15? C. to about 27? C. to form the nickel silicide material.

Cr—Si sintered body

It is difficult for a CrSi-based sintered body composed of chromium silicide (CrSi.sub.2) and silicon (Si) to have high strength. Provided is a CrSi-based sintered body including Cr (chromium) and silicon (Si), in which the crystal structure attributed by X-ray diffraction is composed of chromium silicide (CrSi.sub.2) and silicon (Si), a CrSi.sub.2 phase is present at 60 wt % or more in a bulk, a density of the sintered body is 95% or more, and an average grain size of the CrSi.sub.2 phase is 60 ?m or less.

METHODS OF FORMING METAL SILICIDE LAYERS AND METAL SILICIDE LAYERS FORMED THEREFROM

Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10 and about 50.

Process integration method to tune resistivity of nickel silicide
10388533 · 2019-08-20 · ·

Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a Ni.sub.xSi.sub.1-x layer on the substrate, where x is between about 0.01 and about 0.99.

SILANIZED ITO ELECTRODE WITH ITO NANOPARTICLES FOR AQUEOUS SULFIDE DETECTION

A silanized ITO electrode modified with ITO nanoparticles is described. ITO nanoparticles of cubic and semispherical shapes are immobilized on a silanized ITO film. The electrode may be used in an electrolytic cell to detect aqueous sulfide with a 0.5-1.4 M limit of detection. The electrode shows high specificity towards aqueous sulfide and a high reproducibility in measurement.

Mask blank, phase shift mask, method for manufacturing phase shift mask, and method for manufacturing semiconductor device
10365556 · 2019-07-30 · ·

Provided is a mask blank including a phase shift film on a transparent substrate. This phase shift film includes a phase shift layer at least containing a transition metal and silicon, and a silicon layer, which is configured to attenuate exposure light with which the phase shift layer is irradiated, and the silicon layer is formed to be in contact with the substrate side of the phase shift layer. This mask blank is used in manufacturing a phase shift mask to which laser exposure light having a wavelength of 200 nm or less is applied.

CR-SI FILM
20240175116 · 2024-05-30 ·

A CrSi film contains chromium (Cr) and silicon (Si). In the CrSi film, a composition range of the film is Cr/(Cr+Si)=0.25 to 0.75, and absolute values of TCR in increments of 10? C. in a temperature range of 40? C. to 150? C. are each 0 ppm/? C. or more and 100 ppm/? C. or less.