A method of fabricating a piezoelectric layer includes depositing a piezoelectric material onto a substrate in a first crystallographic phase by physical vapor deposition while the substrate remains at a temperature below 400° C., and thermally annealing the substrate at a temperature above 500° C. to convert the piezoelectric material to a second crystallographic phase. The physical vapor deposition includes sputtering from a target in a plasma deposition chamber.

A method of fabricating a piezoelectric layer includes depositing a piezoelectric material onto a substrate in a first crystallographic phase by physical vapor deposition while the substrate remains at a temperature below 400° C., and thermally annealing the substrate at a temperature above 500° C. to convert the piezoelectric material to a second crystallographic phase. The physical vapor deposition includes sputtering from a target in a plasma deposition chamber.

The present disclosure provides a deposition equipment, which includes a reaction chamber, a carrier, a target material, a magnetic device are at least one shield unit. The carrier and the target material are disposed within the containing space, wherein the carrier is for carrying a substrate, also a surface of the target material faces the carrier and the substrate. The magnetic device is disposed on another surface of the target material, to generate a magnetic field within the containing space through the target material. The shield unit is made electrical conductor and is disposed between a portion of the magnetic device and a portion of the target material, wherein the shield unit is for partially blocking and micro-adjusting the magnetic field generated by the magnetic device within the containing space, such that to improve an evenness of thickness for a thin film formed on the substrate.

A substrate processing system that includes a multi-station processing chamber that includes a plurality of process stations is provided. Each process station has one or more processing components cooled by a cooling system. In one embodiment, the cooling system includes a closed loop monitoring system comprising a flow control valve fluidly coupled to a coolant supply line, a valve position measuring system for continuously monitoring the position of the valve, and a valve position controller for adjusting the position of the valve.

An electronic device and a manufacturing method thereof are provided. The electronic device includes an array substrate, which includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a first sputtering layer, a second sputtering layer, and a third sputtering layer. The second insulating layer is located on the second conductive layer. The second sputtering layer is located between the first and third sputtering layers, and includes a first metal element. The first sputtering layer includes the first metal element and a second metal element. The third sputtering layer includes the first metal element and a third metal element.

In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defined by a processing chamber, and a wafer chuck structure arranged within the processing chamber. The wafer chuck structure is configured to hold a wafer during a fabrication process. The wafer chuck includes a lower portion and an upper portion arranged over the lower portion. The lower portion includes trenches extending from a topmost surface towards a bottommost surface of the lower portion. The upper portion includes openings that are holes, extend completely through the upper portion, and directly overlie the trenches of the lower portion. Multiple of the openings directly overlie each trench. Further, cooling gas piping is coupled to the trenches of the lower portion of the wafer chuck structure, and a cooling gas source is coupled to the cooling gas piping.

A material deposition apparatus for depositing an evaporated material onto a substrate is provided. The material deposition apparatus includes a processing drum having a cooler configured to control a substrate temperature during processing of a substrate on the processing drum; a roller guiding the substrate towards the processing drum; a first heater assembly positioned to heat the substrate in a free-span area between the roller and the processing drum; a second heater assembly positioned to heat the substrate while being supported on the processing drum; at least one deposition source provided along a substrate transport path downstream of the second heater assembly; a substrate speed sensor providing a speed signal correlating with a substrate transportation speed; and a controller having an input for the speed signal configured to control at least the first heater assembly.

A system and method are provided for implementing a unique scheme by which to execute digital vapor phase patterning on metals, semiconductor substrates and other surfaces using a proposed variable data digital lithographic image forming architecture or technique. For certain substrate printing and manufacturing applications, including some printed electronics applications, the disclosed schemes implement techniques to digitally pattern metal layers with bulk material properties in a manner that is aligned with underlying layers on the fly. The disclosed digital printing process may pattern a release oil on a substrate in support of a metal deposition process. Changeable patterning is implemented with an ability to modify the alignment of the patterns on-the-fly. The release layer on a drum is laser patterned in order that the patterned release layer is transferred to the substrate, or the patterning of the release layer is accomplished directly on the substrate.

A system and method are provided for implementing a unique scheme by which to execute digital vapor phase patterning on metals, semiconductor substrates and other surfaces using a proposed variable data digital lithographic image forming architecture or technique. For certain substrate printing and manufacturing applications, including some printed electronics applications, the disclosed schemes implement techniques to digitally pattern metal layers with bulk material properties in a manner that is aligned with underlying layers on the fly. The disclosed digital printing process may pattern a release oil on a substrate in support of a metal deposition process. Changeable patterning is implemented with an ability to modify the alignment of the patterns on-the-fly. The release layer on a drum is laser patterned in order that the patterned release layer is transferred to the substrate, or the patterning of the release layer is accomplished directly on the substrate.

The color of an electrochromic stack in a tinted state may be modified to achieve a desired color target by utilizing various techniques alone or in combination. A first approach generally involves changing a coloration efficiency of a WO.sub.x electrochromic (EC) layer by lowering a sputter temperature to achieve a WO.sub.x microstructural change in the EC layer. A second approach generally involves utilizing a dopant (e.g., Mo, Nb, or V) to improve the neutrality of the tinted state of WO.sub.x (coloration efficiency changes). A third approach generally involves tailoring a thickness of the WO.sub.x layer to tune the color of the tinted stack.