A method includes etching a semiconductor substrate to form a trench, and depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle. The dielectric layer extends into the trench. The ALD cycle includes pulsing Hexachlorodisilane (HCD) to the semiconductor substrate, purging the HCD, pulsing triethylamine to the semiconductor substrate, and purging the triethylamine. An anneal process is then performed on the dielectric layer.

Embodiments of the disclosure include methods and apparatus for electrostatically coupling a mask to a substrate support in a deposition chamber. In one embodiment, a substrate support is disclosed that includes a substrate receiving surface, a recessed portion disposed about a periphery of the substrate receiving surface, an electrostatic chuck disposed below the substrate receiving surface, and a plurality of compressible buttons disposed within a respective opening formed in the recessed portion that form an electrical circuit with the electrostatic chuck.

Embodiments of the present disclosure include positioning a mask over a substrate, wherein the mask has a planar surface separated from a top surface of the substrate by a mask distance, and wherein a mask opening is provided through the planar surface. The method may further include positioning a mask element across the mask opening, the mask element including one or more solid portions and one or more openings, and depositing, through the mask opening, a deposition material onto the substrate, wherein the deposition material has a variable profile as a result of the one or more solid portions and the one or more openings.

A mask assembly includes: a mask frame having a plurality of sides including a first side extending in a first direction, and an opening area defined by the plurality of sides; a gap portion recessed in the first side in a second direction crossing the first direction; a mask sheet covering the opening area; and a gap adjustment portion tensile-welded to the mask frame across the gap portion.

Exemplary processing methods may include flowing a first deposition precursor into a substrate processing region to form a first portion of an initial compound layer. The first deposition precursor may include an aldehyde reactive group. The methods may include removing a first deposition effluent including the first deposition precursor from the substrate processing region. The methods may include flowing a second deposition precursor into the substrate processing region. The second deposition precursor may include an amine reactive group, and the amine reactive group may react with the aldehyde reactive group to form a second portion of the initial compound layer. The methods may include removing a second deposition effluent including the second deposition precursor from the substrate processing region. The methods may include annealing the initial compound layer to form an annealed carbon-containing material on the surface of the substrate.

Provided are a method of depositing a thin film and a method of manufacturing a semiconductor device using the same, and the method of depositing a thin film uses a substrate processing apparatus including a chamber, a substrate support on which a substrate is mounted, a gas supply unit, and a power supply unit that supplies high-frequency and low-frequency power to the chamber, and includes: a step of mounting, on the substrate support, the substrate including a lower thin film deposited under the condition of a process temperature in a low temperature range; a step of depositing an upper thin film on the lower thin film under the condition of the process temperature in the low temperature range; and a step of treating a surface of the upper thin film under the condition of the process temperature in the low temperature range.

A mask strip, comprising: a plurality of mask units (2) in a first direction; each of the mask units (2) comprising a mask region (3) and a non-mask region (11) surrounding the mask region (3), the non-mask region (11) comprising a side region (4) and an original stress concentration region (6) inside the side region (4); each of the mask units (2) further comprising a stress concentration structure, wherein the stress concentration structure is within a part of the side region (4) other than the original stress concentration region (6). Also discloses a mask plate and a method of fabricating a mask strip.

The present disclosure provides a pixel arrangement structure and display panel. The pixel arrangement includes a plurality of pixel repeated combinations. Each of the pixel repeated combinations includes a plurality of pixel units. In the pixel repeated combinations, the plurality of pixel units share a sub-pixel and surround a center of the sub-pixel. By utilizing the present disclosure which makes pixels of the plurality of pixel units sharing one first sub-pixel, the numbers of the first sub-pixels in the pixel arrangement structure and the display panel are reduced, the resolution is enhanced, and fine metal mask (FMM) manufacture technology limitations can be overcome.

Methods of forming metal-containing films by atomic layer deposition are provided. The methods include delivering a metal-containing complex, a purge gas, and a co-reactant to a first substrate under sufficient conditions such that the metal-containing film selectively grows on at least a portion of the first substrate.

A mask assembly includes a mask frame including an edge portion including opposing upper and lower portions along a first direction, and a support which between the upper portion and the lower portion of the edge portion along the first direction; and a mask attachable to the mask frame. The mask includes a pattern area corresponding to the support and including a first welded area at which the mask is attachable to the support, an alignment adjustment pattern adjacent to the first welded area along the first direction, and a second thickness of the mask at the alignment adjustment pattern which is less than a first thickness of the mask at the first welded area, and a first deposition area including upper deposition openings of the mask and between the upper portion and the support of the mask frame.