A mask includes a first sub-mask, a second sub-mask facing the first sub-mask in a first direction and including a boundary surface contacting a boundary surface of the first sub-mask at a boundary portion, and a coupling bar disposed on a lower surface of the first sub-mask and a lower surface of the second sub-mask to connect the first sub-mask to the second sub-mask. Each of the first sub-mask, the second sub-mask, and the coupling bar includes openings. The openings of the coupling bar are aligned with part of the openings of the first and second sub-masks in a thickness direction of the coupling bar.

A method of a growing an embedded single crystal diamond structure, comprising: disposing a single crystal diamond on a non-diamond substrate, wherein the non-diamond substrate is larger than the single crystal diamond; masking a top portion of the single crystal diamond using a masking material; and using a chemical vapor deposition (CVD) growth chamber, growing polycrystalline diamond material surrounding the single crystal diamond in order to join the single crystal diamond to the polycrystalline diamond material.

Embodiments of the present disclosure generally relate to processing an optical workpiece containing grating structures on a substrate by deposition processes, such as atomic layer deposition (ALD). In one or more embodiments, a method for processing an optical workpiece includes positioning a substrate containing a first layer within a processing chamber, where the first layer contains grating structures separated by trenches formed in the first layer, and each of the grating structures has an initial critical dimension, and depositing a second layer on at least the sidewalls of the grating structures by ALD to produce corrected grating structures separated by the trenches, where each of the corrected grating structures has a corrected critical dimension greater than the initial critical dimension.

A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

A microwave plasma chemical vapor deposition device for diamond synthesis. A microwave source generates a microwave signal, and a resonant cavity receives a plurality of process gases. The microwave signal is spread in a first mode at a first waveguide. A mode conversion antenna converts the first mode of the microwave signal into a second mode that is spread at a second waveguide. A coupling conversion cavity receives and transmits the microwave signal in the second mode to the mode conversion antenna thereby converting the second mode of the microwave signal into a third mode. A medium viewport receives the microwave signal in the third mode and transmits to the resonant cavity which enables the microwave signal to excite and discharge the process gases to form spherical plasma, carbon containing groups and atomic hydrogen thereby depositing a diamond film on a seed.

A thin film deposition apparatus used to produce large substrates on a mass scale and improve manufacturing yield. The thin film deposition apparatus includes a deposition source; a first nozzle disposed at a side of the deposition source and including a plurality of first slits arranged in a first direction; a second nozzle disposed opposite to the first nozzle and including a plurality of second slits arranged in the first direction; and a barrier wall assembly including a plurality of barrier walls arranged in the first direction so as to partition a space between the first nozzle and the second nozzle.

The present invention provides an array substrate, an OLED display panel, and a mask. The array substrate includes a predetermined film-forming region and a non-film forming region. The non-film forming region is provided with a shadow region close to the predetermined film-forming region. An actual film forming region of a film layer to be formed on the array substrate includes the predetermined film-forming region and the shadow region. The array substrate is provided with a groove or a protrusion in the corresponding shadow region, so that the film layer is disconnected at the corresponding groove or the protrusion to form a discontinuous film.

A deposition mask unit includes a deposition mask sheet including a plurality of openings, and a deposition mask frame including a raised portion at which the deposition mask sheet is attachable to the deposition mask frame. The raised portion includes a support portion, and a bonding portion protruding from an upper surface of the support portion, an upper surface of the bonding portion being curved.

A structure of a substrate is provided including a tungsten-containing layer including a nucleation layer and a fill layer. The nucleation layer is disposed along sidewalls of the opening. The nucleation layer includes boron and tungsten. The fill layer is disposed over the nucleation layer within the opening. The tungsten-containing layer includes a resistivity of about 16 μΩ.Math.cm or less. The tungsten-containing layer has a thickness of about 200 Å to about 600 Å. The tungsten-containing layer thickness is half a width of the tungsten-containing layer disposed within the opening between opposing sidewall portions of the opening.

The mask includes: a mask body provided with a shielding part configured to shield an IC region between two adjacent panels sharing a base substrate; and the shielding part includes a reinforcing portion and a thinned portion, and the thinned portion has an accommodating recess with an opening facing the base substrate to be configured to accommodate a driving IC in the IC region.