Patent classifications
C23C16/24
SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD OF MANUFACTURING
A semiconductor package assembly and method of manufacturing is provided. The assembly includes a semiconductor package and a moulding resin case encapsulating the semiconductor package. The package includes a lead frame having a first frame side and a second frame side opposite to the first frame side; a silicon die structure having a first die side and a second die side opposite to the first side, the silicon die structure being mounted with its second die side on the first frame side of the lead frame; one or more bond wires electrically connecting the silicon die structure with the lead frame; as well as a coating layer covering the semiconductor package from the encapsulating moulding resin case, the coating layer being composed of two or more different amorphous layer coatings. The use of a coating layer covering the complete semiconductor package forming the encapsulating moulding resin case prevents any corrosion.
SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD OF MANUFACTURING
A semiconductor package assembly and method of manufacturing is provided. The assembly includes a semiconductor package and a moulding resin case encapsulating the semiconductor package. The package includes a lead frame having a first frame side and a second frame side opposite to the first frame side; a silicon die structure having a first die side and a second die side opposite to the first side, the silicon die structure being mounted with its second die side on the first frame side of the lead frame; one or more bond wires electrically connecting the silicon die structure with the lead frame; as well as a coating layer covering the semiconductor package from the encapsulating moulding resin case, the coating layer being composed of two or more different amorphous layer coatings. The use of a coating layer covering the complete semiconductor package forming the encapsulating moulding resin case prevents any corrosion.
MULTI-DEPTH FILM FOR OPTICAL DEVICES
Embodiments of the present disclosure relate to forming multi-depth films for the fabrication of optical devices. One embodiment includes disposing a base layer of a device material on a surface of a substrate. One or more mandrels of the device material are disposed on the base layer. The disposing the one or more mandrels includes positioning a mask over of the base layer. The device material is deposited with the mask positioned over the base layer to form an optical device having the base layer with a base layer depth and the one or more mandrels having a first mandrel depth and a second mandrel depth.
MULTI-DEPTH FILM FOR OPTICAL DEVICES
Embodiments of the present disclosure relate to forming multi-depth films for the fabrication of optical devices. One embodiment includes disposing a base layer of a device material on a surface of a substrate. One or more mandrels of the device material are disposed on the base layer. The disposing the one or more mandrels includes positioning a mask over of the base layer. The device material is deposited with the mask positioned over the base layer to form an optical device having the base layer with a base layer depth and the one or more mandrels having a first mandrel depth and a second mandrel depth.
SUBSTRATE PROCESSING APPARATUS, METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM
There is provided a technique that includes: a cylindrical outer tube; an inner tube that is installed inside the outer tube and configured such that a substrate is capable of being processed in a process chamber formed in the inner tube; a manifold that is installed below the outer tube and the inner tube, in fluid communication with an internal space of the inner tube, and formed in a cylindrical shape with an exhaust space isolated from an annular space between the inner tube and the outer tube; a process gas nozzle configured to supply a process gas that processes the substrate to an inside of the inner tube; a purge gas nozzle configured to supply a purge gas to the annular space; and a conductance changer that is installed at a partition wall between the annular space and the exhaust space.
VAPOR DEPOSITION DEVICE AND METHOD OF PRODUCING EPITAXIAL WAFER
A vapor phase growth system includes a process chamber that includes a susceptor lifting mechanism that raises and lowers the susceptor between a first position and a second position. With the susceptor in the first position, the top surface of the susceptor is above the bottom surface of the preheating ring, and a source gas distribution space with a predetermined height dimension is secured between the top surface of the susceptor and the bottom surface of a ceiling plate of the reaction vessel body. With the susceptor in the second position, the top surface of the susceptor is located below the bottom surface of a preheating ring, and a substrate loading/unloading space, which has a greater height dimension than that of the source gas distribution space, is secured between the top surface of the susceptor and the bottom surface of the preheating ring.
APPARATUS AND METHOD FOR PERFORMING PLASMA ENHANCED ATOMIC LAYER DEPOSITION EMPLOYING VERY HIGH FREQUENCY
The present invention relates to an apparatus and method for forming a silicon nitride film by performing plasma enhanced atomic layer deposition (PE-ALD) employing very high frequency (VHF). An atomic layer deposition apparatus according to an embodiment of the present invention may comprise: a chamber providing a space in which a process is performed; a substrate support unit for supporting a substrate in the chamber; a gas supply unit for supplying gas to the chamber; an exhaust unit for discharging gas in the chamber; a plasma generation unit installed in the chamber to generate plasma in the chamber; and a VHF (very high frequency) power source for applying a VHF band signal to the plasma generation unit.
AMORPHOUS, POROUS SILICON MATERIALS AND RELATED METHODS
Provided herein are Si-based materials, methods of making the Si-based materials, and methods for using the Si-based materials. In embodiments, a silicon-based material comprises an aggregate of particles, the particles comprising an ordered array of nanostructures, the nanostructures comprising amorphous silicon, wherein at least some pairs of adjacent nanostructures are connected by one or more bridges comprising amorphous silicon, the one or more bridges extending from the surface of one nanostructure of the pair to the surface of the other nanostructure in the pair.
AMORPHOUS, POROUS SILICON MATERIALS AND RELATED METHODS
Provided herein are Si-based materials, methods of making the Si-based materials, and methods for using the Si-based materials. In embodiments, a silicon-based material comprises an aggregate of particles, the particles comprising an ordered array of nanostructures, the nanostructures comprising amorphous silicon, wherein at least some pairs of adjacent nanostructures are connected by one or more bridges comprising amorphous silicon, the one or more bridges extending from the surface of one nanostructure of the pair to the surface of the other nanostructure in the pair.
CHEMISTRIES FOR ETCHING MULTI-STACKED LAYERS
Methods for fabricating a 3D NAND flash memory are disclosed. The method includes the steps of forming a hardmask pattern on the hardmask layer, and using the hardmask pattern to form apertures in the alternating layers by selectively plasma etching the alternating layers versus the hardmask layer using a hydrofluorocarbon etching gas selected from the group consisting of 1,1,1,3,3,3-hexafluoropropane (C.sub.3H.sub.2F.sub.6), 1,1,2,2,3,3-hexafluoropropane (iso-C.sub.3H.sub.2F.sub.6), 1,1,1,2,3,3,3-heptafluoropropane (C.sub.3HF.sub.7), and 1,1,1,2,2,3,3-heptafluoropropane (iso-C.sub.3HF.sub.7), wherein the first etching layer comprises a material different from that of the second etching layer.