An MOCVD system for growing a semiconductor layer on a substrate is provided. The MOCVD system includes an MOCVD growth chamber defined by a jacket having an interior surface and an exterior surface; a water flow chamber surrounding an exterior surface of the jacket of the MOCVD growth chamber; an electronic control system, wherein the electronic control system facilitates pulsed growth of the semiconductor layer; a supply tube comprising a head formed from a hollow structure defining a fitting end and an opposite, shower end, wherein the fitting end has an initial diameter that is less than a diameter at the shower end; and a susceptor configured to hold the substrate and facing the shower end of the supply tube, wherein the MOCVD system operates at a temperature greater than or equal to 1500° C.

The present invention proposes a production method for obtainment of three-dimensional closed graphene-based nano-/microstructures (10) using a coaxial multilayer core-shell production process (1000) comprising a coaxial flow system (100) having a first flow path (101) and a first fluid exit (1011) at an end of said first flow path; and a second flow path (102) circumferentially surrounding said first flow path (101), said second flow path having a second fluid exit (1021); wherein a first fluid (1) flows through the first flow path and exits through the first fluid exit (1011); and a second fluid (2) which is immiscible with the first fluid (1) under the conditions where said production method is conducted, flows through the second flow path (102) and exits through the second fluid exit (1021) such that the second fluid (2) circumferentially covers the first fluid (1) upon leaving the coaxial flow system (100); said second fluid (2) comprises a graphene-based material, a polymeric material and solvent.

The present invention proposes a production method for obtainment of three-dimensional closed graphene-based nano-/microstructures (10) using a coaxial multilayer core-shell production process (1000) comprising a coaxial flow system (100) having a first flow path (101) and a first fluid exit (1011) at an end of said first flow path; and a second flow path (102) circumferentially surrounding said first flow path (101), said second flow path having a second fluid exit (1021); wherein a first fluid (1) flows through the first flow path and exits through the first fluid exit (1011); and a second fluid (2) which is immiscible with the first fluid (1) under the conditions where said production method is conducted, flows through the second flow path (102) and exits through the second fluid exit (1021) such that the second fluid (2) circumferentially covers the first fluid (1) upon leaving the coaxial flow system (100); said second fluid (2) comprises a graphene-based material, a polymeric material and solvent.

A low-k dielectric porous silicon oxycarbon layer is formed within an integrated circuit. In one embodiment, a porogen and bulk layer containing silicon oxycarbon layer is deposited, the porogens are selectively removed from the formed layer without simultaneously cross-linking the bulk layer, and then the bulk layer material is cross-linked. In other embodiments, multiple silicon oxycarbon sublayers are deposited, porogens from each sub-layer are selectively removed without simultaneously cross-linking the bulk material of the sub-layer, and the sub-layers are cross-linked separately.

A three-dimensional all-solid-state lithium ion batteries including a cathode protection layer, the battery including: a cathode including a plurality of plates which are vertically disposed on a cathode current collector; a cathode protection layer disposed on a surfaces of the cathode and the cathode current collector; a solid state electrolyte layer disposed on the cathode protection layer; an anode disposed on the solid state electrolyte layer; and an anode current collector disposed on the anode, wherein the cathode protection layer is between the cathode and the solid state electrolyte layer, and wherein the solid state electrolyte layer is between the cathode protection layer and the anode.

Described herein is a method of depositing a plasma resistant ceramic coating onto a surface of a chamber component using a non-line-of-sight (NLOS) deposition process, such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). The plasma resistant ceramic coating consists of an erbium containing oxide, an erbium containing oxy-fluoride, or an erbium containing fluoride. Also described are chamber components having a plasma resistant ceramic coating of an erbium containing oxide, an erbium containing oxy-fluoride, or an erbium containing fluoride.

Described herein is a method of depositing a plasma resistant ceramic coating onto a surface of a chamber component using a non-line-of-sight (NLOS) deposition process, such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). The plasma resistant ceramic coating consists of an erbium containing oxide, an erbium containing oxy-fluoride, or an erbium containing fluoride. Also described are chamber components having a plasma resistant ceramic coating of an erbium containing oxide, an erbium containing oxy-fluoride, or an erbium containing fluoride.

One object of the present invention is to provide a method for producing a metal nitride film that has a high film formation rate and excellent productivity. The present invention provides a method for producing a metal nitride film in which a metal nitride film is formed on at least a part of a surface of a substrate to be processed by chemical vapor deposition using a metal compound raw material and a nitrogen-containing compound raw material, wherein the nitrogen-containing compound raw material contains hydrazine and ammonia.

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N.sub.2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N.sub.2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Methods of enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a dielectric. In some embodiments, a metal surface is functionalized to enhance or decrease its reactivity.