A method of fabricating a composite structure includes providing a c-SiC initial substrate, depositing a relatively thin p-SiC first layer on a front side of the initial substrate at a relatively high temperature, the first layer having a dopant concentration greater than 10.sup.19/cm.sup.3, forming a buried brittle plane in the initial substrate delineating a thin layer of single crystal SiC between the brittle plane and a front side of the initial substrate, depositing a relatively thick amorphous and/or polycrystalline SiC second layer on the first layer at a relatively low temperature, the second layer including dopants of the same type as those of the first layer, at a concentration greater than 10.sup.19/cm.sup.3, and depositing a p-SiC third layer on the second layer at a relatively high temperature. A separation along the buried brittle plane takes place during the deposition process.

A method of fabricating a composite structure includes providing a c-SiC initial substrate, depositing a relatively thin p-SiC first layer on a front side of the initial substrate at a relatively high temperature, the first layer having a dopant concentration greater than 10.sup.19/cm.sup.3, forming a buried brittle plane in the initial substrate delineating a thin layer of single crystal SiC between the brittle plane and a front side of the initial substrate, depositing a relatively thick amorphous and/or polycrystalline SiC second layer on the first layer at a relatively low temperature, the second layer including dopants of the same type as those of the first layer, at a concentration greater than 10.sup.19/cm.sup.3, and depositing a p-SiC third layer on the second layer at a relatively high temperature. A separation along the buried brittle plane takes place during the deposition process.

Various embodiments of wafers include a polycrystalline silicon carbide (SiC) layer or base substrate. The polycrystalline silicon carbide (SiC) layer may have a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter) such that the polycrystalline silicon carbide layer is a low resistivity polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer may have grains with a grain size less than or equal to 1 millimeter (mm), and may have a non-columnar structure. The polycrystalline silicon carbide layer may have a warpage less than or equal to 75 ?m (micrometers). A monocrystalline silicon carbide (SiC) layer may be coupled to the polycrystalline silicon carbide (SiC) layer by a bonding layer. The monocrystalline silicon carbide layer may be thinner than the polycrystalline silicon carbide layer.

Various embodiments of wafers include a polycrystalline silicon carbide (SiC) layer or base substrate. The polycrystalline silicon carbide (SiC) layer may have a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter) such that the polycrystalline silicon carbide layer is a low resistivity polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer may have grains with a grain size less than or equal to 1 millimeter (mm), and may have a non-columnar structure. The polycrystalline silicon carbide layer may have a warpage less than or equal to 75 ?m (micrometers). A monocrystalline silicon carbide (SiC) layer may be coupled to the polycrystalline silicon carbide (SiC) layer by a bonding layer. The monocrystalline silicon carbide layer may be thinner than the polycrystalline silicon carbide layer.

At least one embodiment of a method of manufacturing includes forming a first polycrystalline silicon carbide (SiC) substrate with a sintering process by sintering one or more powdered semiconductor materials. After the first polycrystalline SiC substrate is formed utilizing the sintering process, the first polycrystalline silicon carbide SiC substrate is utilized to form a second polycrystalline SiC substrate with a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on a surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate with the CVD process. As the first and second polycrystalline SiC substrates are made of the same or similar semiconductor material (e.g., SiC), a first coefficient of thermal expansion (CTE) for the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.

At least one embodiment of a method of manufacturing includes forming a first polycrystalline silicon carbide (SiC) substrate with a sintering process by sintering one or more powdered semiconductor materials. After the first polycrystalline SiC substrate is formed utilizing the sintering process, the first polycrystalline silicon carbide SiC substrate is utilized to form a second polycrystalline SiC substrate with a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on a surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate with the CVD process. As the first and second polycrystalline SiC substrates are made of the same or similar semiconductor material (e.g., SiC), a first coefficient of thermal expansion (CTE) for the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.

The present disclosure provides a support tool, for a temporary substrate using a support plate. The support tool includes: a first dummy substrate and a second dummy substrate; and a support, supporting the first dummy substrate and the second dummy substrate, and including at least three of the support plates. The support plate is fitted with the first dummy substrate through a first groove of the plurality of grooves, and fitted with the second dummy substrate through a second groove of the plurality of grooves. The support is configured to support the temporary substrate inserted into a third groove of the plurality of grooves of the support plate excluding the first groove and the second groove.

The present disclosure provides a support tool, for a temporary substrate using a support plate. The support tool includes: a first dummy substrate and a second dummy substrate; and a support, supporting the first dummy substrate and the second dummy substrate, and including at least three of the support plates. The support plate is fitted with the first dummy substrate through a first groove of the plurality of grooves, and fitted with the second dummy substrate through a second groove of the plurality of grooves. The support is configured to support the temporary substrate inserted into a third groove of the plurality of grooves of the support plate excluding the first groove and the second groove.

When FZ single crystal silicon is produced from polycrystalline silicon, which is synthesized by the Siemens method followed by being subjected to thermal treatment and includes crystal grains having a Miller index plane <111> or <220> as a principal plane and grown by the thermal treatment, and in which the X-ray diffraction intensity from either of the Miller index planes <111> and <220> after the thermal treatment is 1.5 times or less the X-ray diffraction intensity before the thermal treatment, as raw material, disappearance of crystal lines in the step of forming an FZ single crystal is markedly prevented.

When FZ single crystal silicon is produced from polycrystalline silicon, which is synthesized by the Siemens method followed by being subjected to thermal treatment and includes crystal grains having a Miller index plane <111> or <220> as a principal plane and grown by the thermal treatment, and in which the X-ray diffraction intensity from either of the Miller index planes <111> and <220> after the thermal treatment is 1.5 times or less the X-ray diffraction intensity before the thermal treatment, as raw material, disappearance of crystal lines in the step of forming an FZ single crystal is markedly prevented.