The present disclosure provides a high purity germanium detector. The high purity germanium detector includes: an array of high purity germanium crystal units including two or more high purity germanium crystal units, wherein, each of the two or more high purity germanium crystal units comprises a partial electrode on a side surface and/or a first top surface, and the electrodes on the side surfaces and/or the first top surfaces of the two or more high purity germanium crystal units are electrically connected together to form a first contact electrode of the high purity germanium detector; and each of the high purity germanium crystal units comprises a respective second contact electrode therein, such that the high purity germanium detector comprises two or more second contact electrodes.

The present disclosure provides a high purity germanium detector. The high purity germanium detector includes: an array of high purity germanium crystal units including two or more high purity germanium crystal units, wherein, each of the two or more high purity germanium crystal units comprises a partial electrode on a side surface and/or a first top surface, and the electrodes on the side surfaces and/or the first top surfaces of the two or more high purity germanium crystal units are electrically connected together to form a first contact electrode of the high purity germanium detector; and each of the high purity germanium crystal units comprises a respective second contact electrode therein, such that the high purity germanium detector comprises two or more second contact electrodes.

An engineered substrate comprising: a seed layer made of a first semiconductor material for growth of a solar cell; a first bonding layer on the seed layer; a support substrate made of a second semiconductor material; a second bonding layer on a first side of the support substrate; a bonding interface between the first and second bonding layers; the first and second bonding layers each made of metallic material; wherein doping concentration and thickness of the engineered substrate, in particular, of the seed layer, the support substrate, and both the first and second bonding layers, are selected such that the absorption of the seed layer is less than 20%, preferably less than 10%, as well as total area-normalized series resistance of the engineered substrate is less than 10 mOhm.Math.cm.sup.2, preferably less than 5 mOhm.Math.cm.sup.2.

A monocrystalline germanium wafer that increases the open-circuit voltage of multijunction solar cells, a method for preparing the monocrystalline germanium wafer and a method for preparing an ingot from which the monocrystalline germanium wafer is prepared. The monocrystalline germanium wafer that increases the open-circuit voltage of the bottom cell of multijunction solar cells is prepared by adjusting the amounts of the co-dopants silicon and gallium in the monocrystalline germanium wafer, the ratio of silicon to gallium in the preparation of the monocrystalline germanium.

A monocrystalline germanium wafer that increases the open-circuit voltage of multijunction solar cells, a method for preparing the monocrystalline germanium wafer and a method for preparing an ingot from which the monocrystalline germanium wafer is prepared. The monocrystalline germanium wafer that increases the open-circuit voltage of the bottom cell of multijunction solar cells is prepared by adjusting the amounts of the co-dopants silicon and gallium in the monocrystalline germanium wafer, the ratio of silicon to gallium in the preparation of the monocrystalline germanium.

A nanowire structure includes a substrate, a patterned mask layer, and a nanowire. The patterned mask layer includes an opening through which the substrate is exposed. Further, the patterned mask layer has a thermal conductivity greater than

[00001]$20\frac{W}{m*K}.$

The nanowire is on the substrate in the opening of the patterned mask layer. By providing the patterned mask layer with a thermal conductivity greater than

[00002]$20\frac{W}{m*K},$

the patterned mask layer is able to maintain a temperature of the surface thereof to a desired level when the nanowire is provided. This prevents undesired parasitic growth on the patterned mask layer, thereby improving the performance of the nanowire structure.

In an embodiment, a method of selectively depositing a silicon germanium material on a substrate is provided. The method includes positioning the substrate within a substrate processing chamber, the substrate having a dielectric material and a silicon containing single crystal thereon; maintaining the substrate at a temperature of about 450° C. or less; exposing the substrate to a process gas comprising: a silicon source gas, a germanium source gas, an etchant gas, a carrier gas, and at least one dopant source gas; and epitaxially and selectively depositing a first silicon germanium material on the substrate.

A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a polycrystalline or amorphous substrate. An electrically conductive Ion Beam-Assisted Deposition (IBAD) template layer is positioned above the substrate. At least one electrically conductive hetero-epitaxial buffer layer is positioned above the IBAD template layer. The at least one buffer layer has a resistivity of less than 100 μΩcm. The semiconductor device and method foster the use of bottom electrodes thereby avoiding complex and expensive lithography processes.

A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a polycrystalline or amorphous substrate. An electrically conductive Ion Beam-Assisted Deposition (IBAD) template layer is positioned above the substrate. At least one electrically conductive hetero-epitaxial buffer layer is positioned above the IBAD template layer. The at least one buffer layer has a resistivity of less than 100 μΩcm. The semiconductor device and method foster the use of bottom electrodes thereby avoiding complex and expensive lithography processes.

A method of forming a semiconductor structure is provided. The method includes etching a trench in a template layer over a substrate, forming a seed structure over a bottom surface of the trench, forming a dielectric cap over the seed structure, and growing a single crystal semiconductor structure within the trench using a vapor liquid solid epitaxy growth process. The single crystal semiconductor structure is grown from a liquid-solid interface between the seed structure and the bottom surface of the trench.