A gas phase nanowire growth apparatus including a reaction chamber, a first input and a second input. The first input is located concentrically within the second input and the first and second input are configured such that a second fluid delivered from the second input provides a sheath between a first fluid delivered from the first input and a wall of the reaction chamber.

Embodiments of the present disclosure include techniques related to techniques for processing materials for manufacture of group-III metal nitride and gallium based substrates. More specifically, embodiments of the disclosure include techniques for growing large area substrates using a combination of processing techniques. Merely by way of example, the disclosure can be applied to growing crystals of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, and others for manufacture of bulk or patterned substrates. Such bulk or patterned substrates can be used for a variety of applications including optoelectronic and electronic devices, lasers, light emitting diodes, solar cells, photo electrochemical water splitting and hydrogen generation, photodetectors, integrated circuits, and transistors, and others.

A method for manufacturing a group III nitride substrate is described. The method involves forming group III nitride films having a group III element face on a surface thereof, on both surfaces of a substrate, so as to produce a group III nitride film carrier. The group III nitride film carrier is subjected to ion implantation and adhered to a base substrate containing polycrystals containing a group III nitride as a major component. The group III nitride film carrier is spaced from the base substrate to transfer the ion-implanted region to the base substrate, so as to form a group III nitride film having an N face on a surface thereof on the base substrate. A group III nitride film is formed on the group III nitride by a THVPE method, so as to produce a thick film of a group III nitride film.

There is provided a Group-III element nitride semiconductor substrate including a first surface and a second surface, in which even when devices to be produced on the first surface are increased in size, variations in device characteristics between the devices in the same substrate are suppressed. A Group-III element nitride semiconductor substrate includes a first surface and a second surface. The Group-III element nitride semiconductor substrate satisfies at least one of the following items (1) to (3): (1) The main surface has a maximum height Wz of a surface waviness profile of 150 nm or less; (2) The main surface has a root mean square height Wq of the surface waviness profile of 25 nm or less; (3) The main surface has an average length WSm of surface waviness profile elements of 0.5 mm or more.

A method for manufacturing a semiconductor structure is provided. The method includes a III-V semiconductor device in a first region of a base substrate and a further device in a second region of the base substrate. The method includes: (a) obtaining a base substrate comprising the first region and the second region, different from the first region; (b) providing a buffer layer over a surface of the base substrate at least in the first region, wherein the buffer layer comprises at least one monolayer of a first two-dimensional layered crystal material; (c) forming, over the buffer layer in the first region, and not in the second region, a III-V semiconductor material; and (d) forming, in the second region, at least part of the further device. A semiconductor structure is also provided.

Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm.sup.−2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm.sup.−2 or less, or 100 cm.sup.−2 or less, or 10 cm.sup.−2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm.sup.−2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm.sup.−2 or less, or 100 cm.sup.−2 or less, or 10 cm.sup.−2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

The problem to be solved by the present invention is to provide a novel technique that can remove a strained layer introduced into an aluminum nitride substrate. In order to solve this problem, the present aluminum nitride substrate manufacturing method involves a strained layer removal step for removing a strained layer in an aluminum nitride substrate by heat treatment of the aluminum nitride substrate in a nitrogen atmosphere. In this way, the present invention can remove a strained layer that has been introduced into an aluminum nitride substrate.

There is provided an aluminum nitride laminate member including: a sapphire substrate having a base surface on which bumps are distributed periodically, each bump having a height of smaller than or equal to 500 nm; and an aluminum nitride layer provided on the base surface and having a surface on which protrusions are formed above the apices of the bumps.

There is provided an aluminum nitride laminate member including: a sapphire substrate having a base surface on which bumps are distributed periodically, each bump having a height of smaller than or equal to 500 nm; and an aluminum nitride layer grown on the base surface and having a flat surface, there being substantially no voids in the aluminum nitride layer.