A sputtering target for a gallium nitride thin film, which has a low oxygen content, a high density and a low resistivity. A gallium nitride powder having powder physical properties of a low oxygen content and a high bulk density is used and hot pressing is conducted at high temperature in high vacuum to prepare a gallium nitride sintered body having a low oxygen content, a high density and a low resistivity.

The present invention relates to: layered gallium arsenide (GaAs), which is more particularly layered GaAs, which, unlike the conventional bulk GaAs, has a two-dimensional crystal structure, has the ability to be easily exfoliated into nanosheets, and exhibits excellent electrical properties by having a structure that enables easy charge transport in the in-plane direction; a method of preparing the same; and a GaAs nanosheet exfoliated from the same.

The present invention relates to: layered gallium arsenide (GaAs), which is more particularly layered GaAs, which, unlike the conventional bulk GaAs, has a two-dimensional crystal structure, has the ability to be easily exfoliated into nanosheets, and exhibits excellent electrical properties by having a structure that enables easy charge transport in the in-plane direction; a method of preparing the same; and a GaAs nanosheet exfoliated from the same.

Embodiments of the present disclosure include techniques related to techniques for processing materials for manufacture of group-III metal nitride and gallium based substrates. More specifically, embodiments of the disclosure include techniques for growing large area substrates using a combination of processing techniques. Merely by way of example, the disclosure can be applied to growing crystals of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, and others for manufacture of bulk or patterned substrates. Such bulk or patterned substrates can be used for a variety of applications including optoelectronic and electronic devices, lasers, light emitting diodes, solar cells, photo electrochemical water splitting and hydrogen generation, photodetectors, integrated circuits, and transistors, and others.

Single crystal CVD diamond material comprising a total nitrogen concentration of at least 5 ppm and a neutral single substitutional nitrogen. N.sub.s.sup.0, to total single substitutional nitrogen, N.sub.s, ratio of at least 0.7. Such a diamond is observed to have a relatively low amount of brown colouration despite the relatively high concentration of nitrogen A method of making the single crystal diamond is also disclosed, the method including growing the CVD diamond in process gases comprising 60 to 200 ppm nitrogen, in addition to a carbon-containing gas, and hydrogen, wherein the ratio of carbon atoms in the carbon-containing gas to hydrogen atoms in the hydrogen gas is 0.5 to 1.5%.

Single crystal CVD diamond material comprising a total nitrogen concentration of at least 5 ppm and a neutral single substitutional nitrogen. N.sub.s.sup.0, to total single substitutional nitrogen, N.sub.s, ratio of at least 0.7. Such a diamond is observed to have a relatively low amount of brown colouration despite the relatively high concentration of nitrogen A method of making the single crystal diamond is also disclosed, the method including growing the CVD diamond in process gases comprising 60 to 200 ppm nitrogen, in addition to a carbon-containing gas, and hydrogen, wherein the ratio of carbon atoms in the carbon-containing gas to hydrogen atoms in the hydrogen gas is 0.5 to 1.5%.

A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.

A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.

Embodiments of the present disclosure generally relate to silicon carbide coated base substrates, silicon carbide substrates thereof, and methods for forming silicon carbide coated base substrates. In some embodiments, a method includes introducing a first silicon-containing precursor to a process chamber at a first temperature of about 800° C. to less than 1,000° C. to form a first silicon carbide layer on a base substrate. The method includes introducing a second silicon-containing precursor, that is the same or different than the first silicon-containing precursor, to the process chamber at a second temperature of about 1,000° C. to about 1,400° C. to form a second silicon carbide layer on the first silicon carbide layer.

Embodiments of the present disclosure generally relate to silicon carbide coated base substrates, silicon carbide substrates thereof, and methods for forming silicon carbide coated base substrates. In some embodiments, a method includes introducing a first silicon-containing precursor to a process chamber at a first temperature of about 800° C. to less than 1,000° C. to form a first silicon carbide layer on a base substrate. The method includes introducing a second silicon-containing precursor, that is the same or different than the first silicon-containing precursor, to the process chamber at a second temperature of about 1,000° C. to about 1,400° C. to form a second silicon carbide layer on the first silicon carbide layer.