Patent classifications
C30B31/22
SEMICONDUCTOR DEVICE
A semiconductor device and a method of manufacturing a semiconductor device according to one or more embodiments are disclosed. An interface layer is formed by implanting ionized impurities into a first layer comprising single-crystalline silicon carbide (SiC). Surfaces of the interface layer and a second layer comprising polycrystalline silicon carbide (SiC) are activated. The activated surfaces of the interface layer and the second layer are contacted and bonded. A covering layer is formed to cover a top surface and sides of the first layer, sides of the interface layer, and sides of the second layer.
SEMICONDUCTOR DEVICE
A semiconductor device and a method of manufacturing a semiconductor device according to one or more embodiments are disclosed. An interface layer is formed by implanting ionized impurities into a first layer comprising single-crystalline silicon carbide (SiC). Surfaces of the interface layer and a second layer comprising polycrystalline silicon carbide (SiC) are activated. The activated surfaces of the interface layer and the second layer are contacted and bonded. A covering layer is formed to cover a top surface and sides of the first layer, sides of the interface layer, and sides of the second layer.
Epitaxial structure of N-face group III nitride, active device, and method for fabricating the same with integration and polarity inversion
The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-Al.sub.yGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-Al.sub.yGaN layer to the junction between the i-GaN channel layer and the i-Al.sub.xGaN layer.
Epitaxial structure of N-face group III nitride, active device, and method for fabricating the same with integration and polarity inversion
The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-Al.sub.yGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-Al.sub.yGaN layer to the junction between the i-GaN channel layer and the i-Al.sub.xGaN layer.
METHOD FOR ON-SILICON INTEGRATION OF A COMPONENT III-V AND ON-SILICON INTEGRATED COMPONENT III-V
A method for on-silicon integration of a III-V-based material component includes providing a first substrate having a silicon-based optical layer including a waveguide, transferring a second substrate of III-V-based material on the optical layer, and forming the III-V component from the second substrate, so as to enable a coupling between the waveguide and the III-V component, by preserving a III-V-based material layer extending laterally. The method also includes forming by epitaxy from the III-V layer, an InP:Fe-based structure laterally bordering the III-V component, forming a layer including contacts configured to contact the III-V component, and transferring a third silicon-based substrate onto the layer including the contacts.
METHOD FOR ON-SILICON INTEGRATION OF A COMPONENT III-V AND ON-SILICON INTEGRATED COMPONENT III-V
A method for on-silicon integration of a III-V-based material component includes providing a first substrate having a silicon-based optical layer including a waveguide, transferring a second substrate of III-V-based material on the optical layer, and forming the III-V component from the second substrate, so as to enable a coupling between the waveguide and the III-V component, by preserving a III-V-based material layer extending laterally. The method also includes forming by epitaxy from the III-V layer, an InP:Fe-based structure laterally bordering the III-V component, forming a layer including contacts configured to contact the III-V component, and transferring a third silicon-based substrate onto the layer including the contacts.
METHOD FOR MANUFACTURING A COMPOSITE STRUCTURE COMPRISING A THIN LAYER MADE OF MONOCRYSTALLINE SIC ON A CARRIER SUBSTRATE MADE OF SIC
A method for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the method comprising: a) a step of providing a donor substrate made of monocrystalline silicon carbide, b) a step of ion implantation of light species into the donor substrate, to form a buried brittle plane delimiting the thin layer between the buried brittle plane and a free surface of the donor substrate, c) a succession of n steps of forming crystalline carrier layers, with n greater than or equal to 2; the n crystalline carrier layers being positioned on the front face of the donor substrate successively one on the other, and forming the carrier substrate; each formation step comprising: direct liquid injection chemical vapor deposition, at a temperature below 900° C., to form a carrier layer, the carrier layer being formed by an at least partially amorphous SiC matrix, and having a thickness of less than or equal to 200 microns; a crystallization heat treatment of the carrier layer, at a temperature of less than or equal to 1000° C., to form a crystalline carrier layer; d) a step of separation along the buried brittle plane, to form, on the one hand, a composite structure comprising the thin layer on the carrier substrate and, on the other hand, the rest of the donor substrate.
METHOD FOR TRANSFERRING A USEFUL LAYER OF CRYSTALLINE DIAMOND ONTO A SUPPORTING SUBSTRATE
Method for transferring a useful layer onto a supporting substrate, comprising the successive steps: a) providing a donor substrate made of crystalline diamond; b) implanting gaseous species, through the first surface of the donor substrate, according to a given implantation dose and implantation temperature suitable for forming a graphitic flat zone; c) assembling the donor substrate to the supporting substrate by direct adhesion; d) applying thermal annealing according to a thermal budget suitable for fracturing the donor substrate along the graphitic flat zone; the annealing temperature being greater than or equal to 800° C.; the implantation temperature is: above a minimum temperature beyond which bubbling of the implanted gaseous species occurs on the first surface when the donor substrate is submitted, in the absence of a stiffening effect, to thermal annealing according to said thermal budget, below a maximum temperature beyond which the given implantation dose no longer allows formation of the graphitic flat zone.
METHOD FOR TRANSFERRING A USEFUL LAYER OF CRYSTALLINE DIAMOND ONTO A SUPPORTING SUBSTRATE
Method for transferring a useful layer onto a supporting substrate, comprising the successive steps: a) providing a donor substrate made of crystalline diamond; b) implanting gaseous species, through the first surface of the donor substrate, according to a given implantation dose and implantation temperature suitable for forming a graphitic flat zone; c) assembling the donor substrate to the supporting substrate by direct adhesion; d) applying thermal annealing according to a thermal budget suitable for fracturing the donor substrate along the graphitic flat zone; the annealing temperature being greater than or equal to 800° C.; the implantation temperature is: above a minimum temperature beyond which bubbling of the implanted gaseous species occurs on the first surface when the donor substrate is submitted, in the absence of a stiffening effect, to thermal annealing according to said thermal budget, below a maximum temperature beyond which the given implantation dose no longer allows formation of the graphitic flat zone.
Multi-step ion implantation
Systems and methods for strengthening a sapphire part are described herein. One embodiment may take the form of a method including orienting a first surface of a sapphire member relative to an ion implantation device and performing a first implantation step. The implanting step may include directing ions at the first surface of the sapphire member to embed them under the first surface. The systems and methods may also include one or more of heating the sapphire member to diffuse the implanted ions into deeper layers of sapphire member, cooling the sapphire member, and performing at least a second implantation step directing ions at the first surface of the sapphire member to embed the ions under the first surface.