An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 μm in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×10.sup.21/cm.sup.3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH.sub.4HF.sub.2) of 7.13% and an ammonium fluoride (NH.sub.4F) of 15.4%.

A laminate including a glass plate and a coating layer, wherein the coating layer includes one or more components selected from the group consisting of silicon nitride, titanium oxide, alumina, niobium oxide, zirconia, indium tin oxide, silicon oxide, magnesium fluoride, and calcium fluoride, wherein a ratio (dc/dg) of a thickness dc of the coating layer to a thickness dg of the glass plate is in a range of 0.05×10.sup.−3 to 1.2×10.sup.−3, and wherein a radius of curvature r1 of the laminate with negating of self-weight deflection is 10 m to 150 m.

This optical article comprises a base material having at least one face coated with an interferential multilayer coating providing either antireflective or high reflective properties. The coating comprises at least one layer of light absorbing material which has an adjustable composition and thickness, such that the visible light mean transmission factor of the coating is controllable to have a value between 95% and 5%.

Disclosed herein are techniques for molding a slanted structure. In some embodiments, a mold for nanoimprint lithography includes a support layer, a polymeric layer on the support layer and including a slanted structure, and an oxide layer on surfaces of the slanted structure. In some embodiments, the oxide layer is conformally deposited on the surfaces of the slanted structure by atomic layer deposition. In some embodiments, the mold further includes an anti-sticking layer on the oxide layer.

Methods for the manufacture of extreme ultraviolet (EUV) mask blanks and production systems therefor are disclosed. A method for forming an EUV mask blank comprises forming a bilayer on a portion of a multi-cathode PVD chamber interior and then forming a multilayer stack of Si/Mo on a substrate in the multi-cathode PVD chamber.

A film forming method is provided in which, when a dielectric film is formed by sputtering a target, the number of particles to get adhered to the surface of a to-be-processed substrate immediately after film formation can be decreased to the extent possible without impairing the function of effectively suppressing the induction of abnormal discharging. A film forming method, according to this invention, of forming a dielectric film on a surface of a to-be-processed substrate by sputtering a target inside a vacuum chamber includes: at the time of sputtering the target, applying negative potential to the target in the form of pulses; and a frequency of applying the negative potential in the form of pulses is set to a range of 100 kHz or more and 150 kHz or below and an application time (Ton) of the negative potential is set to a range of 5 μsec or longer and 8 μsec or shorter.

The use of non-mass analyzed ion implanter is advantageous in such application as it generates ion implanting at different depth depending on the ions energy and mass. This allows for gaining advantage from lubricity offered as a result of the very light deposition on the surface, and at the same time the hardness provided by the intercalated ions implanted below it, providing benefits for cover glass, low E enhancement, and other similar materials. In further aspects, ion implantation is used to create other desirable film properties such anti-microbial and corrosion resistance.

Electrochromic devices and methods may employ the addition of a defect-mitigating insulating layer which prevents electronically conducting layers and/or electrochromically active layers from contacting layers of the opposite polarity and creating a short circuit in regions where defects form. In some embodiments, an encapsulating layer is provided to encapsulate particles and prevent them from ejecting from the device stack and risking a short circuit when subsequent layers are deposited. The insulating layer may have an electronic resistivity of between about 1 and 10.sup.8 Ohm-cm. In some embodiments, the insulating layer contains one or more of the following metal oxides: aluminum oxide, zinc oxide, tin oxide, silicon aluminum oxide, cerium oxide, tungsten oxide, nickel tungsten oxide, and oxidized indium tin oxide. Carbides, nitrides, oxynitrides, and oxycarbides may also be used.

The invention relates to a method for coating a substrate 40, a coating system for carrying out the method, and a coated body. In a first method step 62, the substrate 40 is to pretreated in a ion etching process. In a second method step 64, a first coating layer 56a with a thickness of 0.1 μm to 6 μm is deposited on the substrate 40 by means of a PVD process. In order to achieve a particularly high-quality and durable coating 50, the surface of the first coating layer 56a is treated by means of an ion etching process in a third method step 66, and an additional coating layer 56b with a thickness of 0.1 μm to 6 μm is deposited on the first coating layer 56a by means of a PVD process in a fourth method step 68. The coated body comprises at least two coating layers 56a, 56b, 56c, 56d with a thickness of 0.1 μm to 6 μm on a substrate 40, wherein an interface region formed by ion etching is arranged between the coating layers 56a, 56b, 56c, 56d.

Transistors and method of forming he same include forming a fin on a bottom source/drain region having a channel region and a sacrificial region on the channel region. A gate stack is formed on sidewalls of the channel region. A gate conductor is formed in contact with the gate stack that has a top surface that meets a middle point of sidewalls of the sacrificial region. The sacrificial region is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor having airgaps above the gate stack.