A ceramic circuit substrate is suitable for silver nanoparticle bonding of semiconductor elements and has excellent close adhesiveness with a power module sealing resin. A ceramic circuit substrate has a copper plate bonded, by a braze material, to both main surfaces of a ceramic substrate including aluminum nitride or silicon nitride, the copper plate of at least one of the main surfaces being subjected to silver plating, wherein: the copper plate side surfaces are not subjected to silver plating; the thickness of the silver plating is 0.1 μm to 1.5 μm; and the arithmetic mean roughness Ra of the surface roughness of the circuit substrate after silver plating is 0.1 μm to 1.5 μm.

Compositions and methods for silver plating onto metal surfaces such as PWBs in electronics manufacture to produce a silver plating which is greater than 80 atomic % silver, tarnish resistant, and has good solderability.

Compositions and methods for silver plating onto metal surfaces such as PWBs in electronics manufacture to produce a silver plating which is greater than 80 atomic % silver, tarnish resistant, and has good solderability.

Chemical vapor deposition (CVD) processes which use a ruthenium precursor of formula R.sup.1R.sup.2Ru(0), wherein R.sup.1 is an aryl group-containing ligand, and R.sup.2 is a diene group-containing ligand and a reducing gas a described. The CVD can include oxygen after an initial deposition period using the ruthenium precursor and reducing gas. The method can provide selective Ru deposition on conductive materials while minimizing deposition on non-conductive or less conductive materials. Further, the subsequent use of oxygen can significantly improve deposition rate while minimizing or eliminating oxidative damage of the substrate material. The method can be used to form Ru-containing layers on integrated circuits and other microelectronic devices.

Chemical vapor deposition (CVD) processes which use a ruthenium precursor of formula R.sup.1R.sup.2Ru(0), wherein R.sup.1 is an aryl group-containing ligand, and R.sup.2 is a diene group-containing ligand and a reducing gas a described. The CVD can include oxygen after an initial deposition period using the ruthenium precursor and reducing gas. The method can provide selective Ru deposition on conductive materials while minimizing deposition on non-conductive or less conductive materials. Further, the subsequent use of oxygen can significantly improve deposition rate while minimizing or eliminating oxidative damage of the substrate material. The method can be used to form Ru-containing layers on integrated circuits and other microelectronic devices.

Provided is a silicon bulk thermoelectric conversion material in which thermoelectric performance is improved by reducing the thermal conductivity as compared with the prior art. In the silicon bulk thermoelectric conversion material, the ZT is greater than 0.2 at room temperature with the elemental silicon. In the silicon bulk thermoelectric conversion material, a plurality of silicon grains have an average of 1 nm or more and 300 nm or less, a first hole have an average of 1 nm or more and 30 nm or less present in the plurality of silicon grains and surfaces of the silicon grains, and a second hole have an average of 100 nm or more and 300 nm or less present between the plurality of silicon grains, wherein the aspect ratio of a crystalline silicon grain is less than 10.

Metalized plastic substrates, and methods thereof are provided herein. The method includes providing a plastic substrate having a plurality of accelerators dispersed in the plastic substrate. The accelerators have a formula selected from the group consisting of: CuFe.sub.2O.sub.4−δ, Ca.sub.0.25Cu.sub.0.75TiO.sub.3−β, and TiO.sub.2−σ, wherein δ, β, σ denotes oxygen vacancies in corresponding accelerators and 0.05≦δ≦0.8, 0.05≦β≦0.5, and 0.05≦σ≦1.0. The method further includes removing at least a portion of a surface of the plastic substrate to expose at least a first accelerator. The method further includes plating the exposed surface of the plastic substrate to form at least a first metal layer on the at least first accelerator, and then plating the first metal layer to form at least a second metal layer.

Metalized plastic substrates, and methods thereof are provided herein. The method includes providing a plastic substrate having a plurality of accelerators dispersed in the plastic substrate. The accelerators have a formula selected from the group consisting of: CuFe.sub.2O.sub.4−δ, Ca.sub.0.25Cu.sub.0.75TiO.sub.3−β, and TiO.sub.2−σ, wherein δ, β, σ denotes oxygen vacancies in corresponding accelerators and 0.05≦δ≦0.8, 0.05≦β≦0.5, and 0.05≦σ≦1.0. The method further includes removing at least a portion of a surface of the plastic substrate to expose at least a first accelerator. The method further includes plating the exposed surface of the plastic substrate to form at least a first metal layer on the at least first accelerator, and then plating the first metal layer to form at least a second metal layer.

A heat dissipation component for a semiconductor element includes: a composite part containing 50-80 vol % diamond powder with the remainder having metal including aluminum, the diamond powder having a particle diameter volume distribution first peak at 5-25 μm and a second peak at 55-195 μm. A ratio between a volume distribution area at particle diameters of 1-35 μm and a volume distribution area at particle diameters of 45-205 μm is 1:9 to 4:6; surface layers on both composite part principal surfaces, each of the surface layers containing 80 vol % or more metal including aluminum and having a film thickness of 0.03-0.2 mm; and a crystalline Ni layer and an Au layer on at least one of the surface layers, the crystalline Ni layer having a film thickness of 0.5-6.5 μm, and the Au layer having a film thickness of 0.05 μm or larger.

A semiconductor substrate has, on an Au electrode pad, an electrolessly-plated Ni film/an electrolessly-plated Pd film/an electrolessly-plated Au film or an electrolessly-plated Ni film/an electrolessly-plated Au film and a method of manufacturing the semiconductor substrate by the steps indicated in (1) to (6) below: (1) a degreasing step; (2) an etching step; (3) a pre-dipping step; (4) a Pd catalyst application step; (5) an electroless Ni plating step; (6) an electroless Pd plating step and electroless Au plating step or an electroless Au plating step.