Patent classifications
C30B25/183
Method of manufacturing group III nitride semiconductor substrate, group III nitride semiconductor substrate, and bulk crystal
There is provided a method of manufacturing a group III nitride semiconductor substrate including: a fixing step S10 of fixing abase substrate, which includes a group III nitride semiconductor layer having a semipolar plane as a main surface, to a susceptor; a first growth step S11 of forming a first growth layer by growing a group III nitride semiconductor over the main surface of the group III nitride semiconductor layer in a state in which the base substrate is fixed to the susceptor using an HVPE method; a cooling step S12 of cooling a laminate including the susceptor, the base substrate, and the first growth layer; and a second growth step S13 of forming a second growth layer by growing a group III nitride semiconductor over the first growth layer in a state in which the base substrate is fixed to the susceptor using the HVPE method.
Superconducting compounds and methods for making the same
A superconducting article includes a substrate and a superconducting metal oxide film formed on the substrate. The metal oxide film including ions of an alkali metal, ions of a transition metal, and ions of an alkaline earth metal or a rare earth metal. For instance, the metal oxide film can include Rb ions, La ions, and Cu ions. The superconducting metal oxide film can have a critical temperature for onset of superconductivity of greater than 250 K, e.g., greater than room temperature.
EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICES, ELECTRONIC DEVICE, METHOD FOR PRODUCING THE EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICES, AND METHOD FOR PRODUCING THE ELECTRONIC DEVICE
An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.
Method of high growth rate deposition for group III/V materials
Embodiments of the invention generally relate processes for epitaxial growing Group III/V materials at high growth rates, such as about 30 μm/hr or greater, for example, about 40 μm/hr, about 50 μm/hr, about 55 μm/hr, about 60 μm/hr, or greater. The deposited Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.
III-V or II-VI compound semiconductor films on graphitic substrates
A composition of matter comprising a film on a graphitic substrate, said film having been grown epitaxially on said substrate, wherein said film comprises at least one group III-V compound or at least one group II-VI compound.
GROUP III NITRIDE STACK
There is provided a Group III nitride stack in which the concentration of an impurity in the buffer/channel layer of an HEMT is suppressed to a predetermined range. The Group III nitride stack includes a first layer comprising gallium nitride, and a second layer on the first layer, the second layer comprising a Group III nitride having a lower electron affinity than gallium nitride. The first layer includes a lower layer and an upper layer on the lower layer. The carbon concentration in the upper layer is lower than a carbon concentration in the lower layer, the hydrogen concentration in the upper layer is lower than a hydrogen concentration in the lower layer, the carbon concentration in the upper layer is 5×10.sup.16 cm.sup.−3 or less, and the hydrogen concentration in the upper layer is 1×10.sup.17 cm.sup.−3 or less.
GROUP III NITRIDE SEMICONDUCTOR, AND METHOD FOR PRODUCING SAME
On an RAMO.sub.4 substrate containing a single crystal represented by the general formula RAMO.sub.4 (wherein R represents one or a plurality of trivalent elements selected from a group of elements including: Sc, In, Y, and a lanthanoid element, A represents one or a plurality of trivalent elements selected from a group of elements including: Fe(III), Ga, and Al, and M represents one or a plurality of divalent elements selected from a group of elements including: Mg, Mn, Fe(II), Co, Cu, Zn, and Cd), a buffer layer containing a nitride of In and a Group III element except for In is formed, and a Group III nitride crystal is formed on the buffer layer.
Structures and devices including germanium-tin films and methods of forming same
Methods of forming germanium-tin films using germane as a precursor are disclosed. Exemplary methods include growing films including germanium and tin in an epitaxial chemical vapor deposition reactor, wherein a ratio of a tin precursor to germane is less than 0.1. Also disclosed are structures and devices including germanium-tin films formed using the methods described herein.
Stress mitigating amorphous SiO2 interlayer
A method of forming a REO dielectric layer and a layer of a-Si between a III-N layer and a silicon substrate. The method includes depositing single crystal REO on the substrate. The single crystal REO has a lattice constant adjacent the substrate matching the lattice constant of the substrate and a lattice constant matching a selected III-N material adjacent an upper surface. A uniform layer of a-Si is formed on the REO. A second layer of REO is deposited on the layer of a-Si with the temperature required for epitaxial growth crystallizing the layer of a-Si and the crystallized silicon being transformed to amorphous silicon after transferring the lattice constant of the selected III-N material of the first layer of REO to the second layer of REO, and a single crystal layer of the selected III-N material deposited on the second layer of REO.
NUCLEATION LAYER DEPOSITION METHOD
A nucleation layer comprised of group III and V elements is directly deposited onto the surface of a substrate made of a group IV element. Together with a first gaseous starting material containing a group III element, a second gaseous starting material containing a group V element is introduced at a process temperature of greater than 500° C. into a process chamber containing the substrate. It is essential that at least at the start of the deposition process of the nucleation layer, a third gaseous starting material containing a group IV element is fed into the process chamber, together with the first and second gaseous starting material. The third gaseous starting material develops an n-doping effect in the deposited III-V crystal, which causes a decrease in damping at a dopant concentration of less than 1×10.sup.18 cm.sup.−3.