C30B29/403

MANUFACTURING METHOD OF MODIFIED ALUMINUM NITRIDE RAW MATERIAL, MODIFIED ALUMINUM NITRIDE RAW MATERIAL, MANUFACTURING METHOD OF ALUMINUM NITRIDE CRYSTALS, AND DOWNFALL DEFECT PREVENTION METHOD

The purpose of the present is to provide a modified AlN source for suppressing downfall defects. This manufacturing method of a modified aluminum nitride source involves a heat treatment step for heat treating an aluminum nitride source and generating an aluminum nitride sintered body.

MANUFACTURING METHOD OF SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND SEMICONDUCTOR LIGHT-EMITTING ELEMENT
20170317234 · 2017-11-02 · ·

There are provided a setting process configured to set in a chamber an aluminum nitride substrate in which a semiconductor layer is formed on a first principal plane, and an oxide film forming process configured to heat an inside of the chamber with a water molecule (H.sub.2O) being introduced in the chamber and to form an oxide film including an amorphous oxide film and/or a crystalline oxide film on a second principal plane located on an opposite side to the first principal plane of the aluminum nitride substrate.

POLYCRYSTALLINE CERAMIC SUBSTRATE AND METHOD OF MANUFACTURE
20220059341 · 2022-02-24 · ·

An engineered substrate structure includes a ceramic substrate having a front surface characterized by a plurality of peaks. The ceramic substrate includes a polycrystalline material. The engineered substrate structure also includes a planarization layer comprising a planarization layer material and coupled to the front surface of the ceramic substrate. The planarization layer defines fill regions filled with the planarization layer material between adjacent peaks of the plurality of peaks on the front surface of the ceramic substrate. The engineered substrate structure further includes a barrier shell encapsulating the ceramic substrate and the planarization layer, wherein the barrier shell has a front side and a back side, a bonding layer coupled to the front side of the barrier shell, a single crystal layer coupled to the bonding layer, and a conductive layer coupled to the back side of the barrier shell.

Piezoelectric member that achieves high sound speed, acoustic wave apparatus, and piezoelectric member manufacturing method

A piezoelectric member that achieves a high sound speed includes a silicon-containing substrate and a piezoelectric layer. The piezoelectric layer is disposed on the silicon-containing substrate. At least a surface layer of the piezoelectric layer on a side opposite to the silicon-containing substrate is made of B.sub.xAl.sub.1-xN (0<x≦0.2).

METHOD OF MANUFACTURING GROUP-III NITRIDE CRYSTAL

A method of manufacturing a group-III nitride crystal includes: preparing a seed substrate; and supplying a group-III element oxide gas and a nitrogen element-containing gas at a supersaturation ratio (P.sup.o/P.sup.e) greater than 1 and equal to or less than 5, then, growing a group-III nitride crystal on the seed substrate, wherein the P.sup.o is a supply partial pressure of the group-III element oxide gas, and the P.sup.e is an equilibrium partial pressure of the group-III element oxide gas.

EPITAXIAL FILM FORMING METHOD, SPUTTERING APPARATUS, MANUFACTURING METHOD OF SEMICONDUCTOR LIGHT-EMITTING ELEMENT, SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND ILLUMINATION DEVICE
20170309480 · 2017-10-26 ·

The present invention provides an epitaxial film forming method for epitaxially growing a high-quality group III nitride semiconductor thin film on an α-Al.sub.2O.sub.3 substrate by a sputtering method. In the epitaxial film forming method according to an embodiment of the present invention, when an epitaxial film of a group III nitride semiconductor thin film is to be formed on the α-Al.sub.2O.sub.3 substrate arranged on a substrate holder provided with a heater electrode and a bias electrode of a sputtering apparatus, in a state where the α-Al.sub.2O.sub.3 substrate is maintained at a predetermined temperature by the heater electrode, high-frequency power is applied to a target electrode and high-frequency bias power is applied to a bias electrode and at that time, the powers are applied so that frequency interference between the high-frequency power and the high-frequency bias power does not occur.

SUBSTRATE WAFER AND MANUFACTURING METHOD OF A III-NITRIDE SEMICONDUCTOR DEVICE

A substrate wafer composed of a hexagonal single crystal material including a C crystalline plane, an A crystalline plane, and an M-axis direction includes a top surface is a C-axis plane; a first side connecting to the aforementioned top surface and being substantially a curve line viewing from the direction perpendicular to the aforementioned C crystalline plane and including a curvature center; and a second side connecting to the aforementioned first side; and wherein there is a line segment defined by a shortest distance between the aforementioned second side and the aforementioned curvature center, and the aforementioned line segment is not parallel with the aforementioned M-axis direction.

Technique for the growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices

A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Group III nitride bulk crystals and their fabrication method

In one instance, the invention provides a bulk crystal of group III nitride having a thickness of more than 1 mm without cracking above the sides of a seed crystal. This bulk group III nitride crystal is expressed as Ga.sub.x1Al.sub.y1In.sub.1-x1-y1N (0≦x1≦1, 0≦x1+y1≦1) and the seed crystal is expressed as Ga.sub.x2Al.sub.y2In.sub.1-x2-y2N (0≦x2≦1, 0≦x2+y2≦1). The bulk crystal of group III nitride can be grown in supercritical ammonia or a melt of group III metal using at least one seed crystal having basal planes of c-orientation and sidewalls of m-orientation. By exposing only c-planes and m-planes in this instance, cracks originating from the sides of the seed crystal are avoided.

Stress mitigating amorphous SiO2 interlayer
09824886 · 2017-11-21 · ·

A method of forming a REO dielectric layer and a layer of a-Si between a III-N layer and a silicon substrate. The method includes depositing single crystal REO on the substrate. The single crystal REO has a lattice constant adjacent the substrate matching the lattice constant of the substrate and a lattice constant matching a selected III-N material adjacent an upper surface. A uniform layer of a-Si is formed on the REO. A second layer of REO is deposited on the layer of a-Si with the temperature required for epitaxial growth crystallizing the layer of a-Si and the crystallized silicon being transformed to amorphous silicon after transferring the lattice constant of the selected III-N material of the first layer of REO to the second layer of REO, and a single crystal layer of the selected III-N material deposited on the second layer of REO.