A multi-layer thin film composite is formed by applying a thin film formed from non-single-crystalline oxide onto a substrate; applying a protection film onto the thin film; and supplying energy to the thin film through at least one of the protection film or the substrate.

A multi-layer thin film composite is formed by applying a thin film formed from non-single-crystalline oxide onto a substrate; applying a protection film onto the thin film; and supplying energy to the thin film through at least one of the protection film or the substrate.

A multi-layer thin film composite is formed by applying a thin film formed from non-single-crystalline oxide onto a substrate; applying a protection film onto the thin film; and supplying energy to the thin film through at least one of the protection film or the substrate.

Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm.sup.−2, and a resistivity of 1×10.sup.7 Ω-cm or more. The wafer may have an optical absorption of less than 5 cm.sup.−1 less than 4 cm.sup.−1 or less than 3 cm.sup.−1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm.sup.2/V-sec or higher. The wafer may have a thickness of 500 μm or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×10.sup.7 cm.sup.−3 or less.

Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm.sup.−2, and a resistivity of 1×10.sup.7 Ω-cm or more. The wafer may have an optical absorption of less than 5 cm.sup.−1 less than 4 cm.sup.−1 or less than 3 cm.sup.−1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm.sup.2/V-sec or higher. The wafer may have a thickness of 500 μm or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×10.sup.7 cm.sup.−3 or less.

Embodiments of the invention generally relate processes for epitaxial growing Group III/V materials at high growth rates, such as about 30 μm/hr or greater, for example, about 40 μm/hr, about 50 μm/hr, about 55 μm/hr, about 60 μm/hr, or greater. The deposited Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.

Embodiments of the invention generally relate processes for epitaxial growing Group III/V materials at high growth rates, such as about 30 μm/hr or greater, for example, about 40 μm/hr, about 50 μm/hr, about 55 μm/hr, about 60 μm/hr, or greater. The deposited Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.

Dust that is accumulated in an exhaust passage provided in a chamber, the exhaust passage for discharging gas in the chamber of a semiconductor crystal manufacturing device, is removed by being sucked from the outside of the chamber. Moreover, an opening and closing valve for cleaning that is detachably attached to an opening of the exhaust passage, the opening facing the chamber, is opened and closed intermittently in a suction state. Furthermore, the opening and closing valve for cleaning is driven by a valve driving unit. The dust accumulated in the exhaust passage is removed efficiently, whereby the time required to clean the exhaust passage is shortened and fluctuations of the pressure inside the chamber when a semiconductor crystal is manufactured are suppressed.

An engineered substrate comprising: a seed layer made of a first semiconductor material for growth of a solar cell; a first bonding layer on the seed layer; a support substrate made of a second semiconductor material; a second bonding layer on a first side of the support substrate; a bonding interface between the first and second bonding layers; the first and second bonding layers each made of metallic material; wherein doping concentration and thickness of the engineered substrate, in particular, of the seed layer, the support substrate, and both the first and second bonding layers, are selected such that the absorption of the seed layer is less than 20%, preferably less than 10%, as well as total area-normalized series resistance of the engineered substrate is less than 10 mOhm.Math.cm.sup.2, preferably less than 5 mOhm.Math.cm.sup.2.

Thin freestanding nitride veneers can be used for the fabrication of semiconductor devices. These veneers are typically less than 100 microns thick. The use of thin veneers also eliminates the need for subsequent wafer thinning for improved thermal performance and 3D packaging.