Methods of forming a metallic-ceramic brazed joint are disclosed herein. The method of forming the brazed joint includes deoxidizing the surface of metallic components, assembling the joint, heating the joint to fuse the joint components, and cooling the joint. In certain embodiments, the brazed joint includes a conformal layer. In further embodiments, the brazed joint has features in order to reduce stress concentrations within the joint.

According to an aspect of the invention, there is provided a plasma-resistant member including: a base member; and a layer structural component formed at a surface of the base member, the layer structural component including an yttria polycrystalline body and being plasma resistant, the layer structural component including a first uneven structure, and a second uneven structure formed to be superimposed onto the first uneven structure, the second uneven structure having an unevenness finer than an unevenness of the first uneven structure.

A method for producing a metal-ceramic substrate with electrically conductive vias includes: attaching a first metal layer in a planar manner to a first surface side of a ceramic layer; after attaching the first metal layer, introducing a copper hydroxide or copper acetate brine into holes in the ceramic layer delimiting a via, to form an assembly; converting the copper hydroxide or copper acetate brine into copper oxide; subjecting the assembly to a high-temperature step above 500° C. in which the copper oxide forms a copper body in the holes; and after converting the copper hydroxide or copper acetate brine into the copper oxide, attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side. The copper body produces an electrically conductive connection between the first and the second metal layers.

A component for use in a semiconductor processing chamber is provided. A component body of a dielectric material has a semiconductor processing facing surface. A coating of a dielectric material is on at least the semiconductor processing facing surface, wherein the dielectric material of the component body has a same stoichiometry as the dielectric material of the coating.

Disclosed is a joined ceramic body comprising a first ceramic portion comprising a first ceramic, a second ceramic portion comprising a second ceramic, and a joining layer formed between the first ceramic portion and the second ceramic portion. The joining layer has a bond thickness of from 0.5 to 20 um and comprises silicon dioxide having a total impurity content of 20 ppm and less. A method of making the joined ceramic body and a joining material are also disclosed.

Provided is at least any of a layered body, which has a change in texture derived from zirconia, particularly a change in translucency and is suitable as a dental prosthetic member, a precursor thereof, or a method for producing these. There is provided a layered body having a structure in which two or more layers containing zirconia containing a stabilizer are layered, the layered body including at least: a first layer containing zirconia having a stabilizer content of higher than or equal to 4 mol %; and a second layer containing zirconia having a stabilizer content different from that of the zirconia contained in the first layer.

Disclosed is a method for manufacturing a ceramic susceptor, the method including: preparing ceramic sheets; preparing a lamination structure of a molded body, in which the ceramic sheets are laminated and a conductive metal layer for electrodes is disposed between the ceramic sheet laminated products; and sintering the lamination structure of the molded body, wherein the preparing of the ceramic sheets includes: obtaining a vitrified first additive powder by heat-treating a slurry containing MgO, SiO.sub.2, and CaO; preparing a slurry by mixing an Al.sub.2O.sub.3 powder with the first additive powder, a second additive powder containing a MgO powder, and a third additive powder containing a Y.sub.2O.sub.3 powder; and forming the ceramic sheets by tape casting the slurry.

Proposed are a laminated anodic aluminum oxide structure in which a plurality of anodic aluminum oxide films are stacked, a guide plate of a probe card using the same, and a probe card having the same. More particularly, proposed are a laminated anodic aluminum oxide structure with a high degree of surface strength, a guide plate of a probe card using the same, and a probe card having the same.

An airfoil including a plurality of composite plies extending from a leading edge to a trailing edge and between a tip and a root. The airfoil further includes a frangible airfoil portion at the tip extending between the leading edge and the trailing edge and extending between the tip and a frangible line along a span including a first plurality of composite plies. The frangible airfoil portion includes a first plurality of composite plies including fibers having a first fiber modulus. The airfoil further includes a residual airfoil portion extending from the frangible line to the root along the span including a second plurality of composite plies. The second plurality of composite plies including one or more plies having a second fiber modulus. The second fiber modulus is greater than the first fiber modulus. Further, the residual airfoil portion meets the frangible airfoil portion at the frangible line.

Provided is a polycrystalline ceramic substrate to be bonded to a compound semiconductor substrate with a bonding layer interposed therebetween, wherein at least one of relational expression (1) 0.7<α.sub.1/α.sub.2<0.9 and relational expression (2) 0.7<α.sub.3/α.sub.4<0.9 holds, where α.sub.1 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 300° C. and α.sub.2 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 300° C., and α.sub.3 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 1000° C. and α.sub.4 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 1000° C.