Chucks for supporting semiconductor wafers during certain processing operations are disclosed. The chucks may include a recessed region near the outer perimeter of the wafer that has one or more surfaces that face towards the wafer but are recessed therefrom so as to not contact the wafer around the perimeter of the wafer. The use of such a recessed region prevents direct thermally conductive contact between the chuck and the wafer, thereby allowing the wafer to achieve a more uniform temperature distribution in certain process conditions. This has the further effect of causing certain processing operations to be more uniform with respect to edge-center deposition (or etch) layer thickness.

Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support disposed within the chamber body. The substrate support may define a substrate support surface. The chambers may include a showerhead positioned supported atop the chamber body. The substrate support and a bottom surface of the showerhead may at least partially define a processing region within the semiconductor processing chamber. The showerhead may define a plurality of apertures through the showerhead. The bottom surface of the showerhead may define an annular groove or ridge that is positioned directly above at least a portion of the substrate support.

Provided are apparatuses and methods for performing deposition and etch processes in an integrated tool. An apparatus may include a plasma processing chamber that is a capacitively-coupled plasma reactor, and the plasma processing chamber can include a showerhead that includes a top electrode and a pedestal that includes a bottom electrode. The apparatus may be configured with an RF hardware configuration so that an RF generator may power the top electrode in a deposition mode and power the bottom electrode in an etch mode. In some implementations, the apparatus can include one or more switches so that at least an HFRF generator is electrically connected to the showerhead in a deposition mode, and the HFRF generator and an LFRF generator is electrically connected to the pedestal and the showerhead is grounded in the etch mode.

A system includes an electrode. The electrode includes a showerhead having a first stem portion and a head portion. A plurality of dielectric layers is vertically stacked between the electrode and a first surface of a conducting structure. The plurality of dielectric layers includes M dielectric layers arranged adjacent to the head portion and P dielectric portions arranged around the first stem portion. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap, and the third gap are selected to prevent parasitic plasma between the first surface and the electrode.

Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

An alignment device is provided to draw two components together in an aligned configuration. An example alignment device comprises a planetary gear set including a ring gear and at least two planetary gears and one or more side plates for supporting the gears. Each of the planetary gears includes an aperture sized to receive a threaded fastener for engagement with a respective threaded rod that is engaged with one of the two components, wherein rotation of the ring gear imparts rotational movement to the threaded fasteners to cause synchronized advancement of the alignment device along the threaded rods.

Additively manufactured showerheads for semiconductor processing operations are disclosed that may have various features enabled by the use of such manufacturing techniques. In some implementations, such showerheads may have multiple independent flow paths featuring transverse passages arranged to form a rhombic lattice pattern and gas distribution ports and/or riser passages that are located at various intersections between such transverse passages. Such showerheads may also include features that improve their manufacturability while providing desired gas flow performance. For example, the cross-sections of the transverse passages may be designed such that they are generally triangular or pentagonal in shape, which may allow for more efficient use of available material volume within the showerhead for the purposes of providing gas flow passages while also providing geometries that take into account the limitations of typical additive manufacturing processes that may be used.

A two-dimensional layer is deposited onto a substrate in a CVD reactor, in which a process gas is fed into a process chamber. The process gas in the process chamber is brought to the substrate, and the substrate is heated to a process temperature. After a chemical reaction of the process gas, the layer forms on the surface. During or after the heating of the substrate to the process temperature, the process gas with a first mass flow rate is initially fed into the process chamber and then, while the substrate surface is being observed, the mass flow rate of the process gas is increased to a rate at which the layer growth begins, and subsequently the mass flow rate of the process gas is increased by a predetermined value, during which the layer is deposited. The beginning of the layer growth is identified by observing measurements from a pyrometer.

Methods and apparatuses are provided herein for oxidizing an annular edge region of a substrate. A method may include providing the substrate to a substrate holder in a semiconductor processing chamber, the semiconductor processing chamber having a showerbead positioned above the substrate holder, and simultaneously flowing, while the substrate is supported by the substrate holder, (a) an oxidizing gas around a periphery of the substrate and (b) an inert gas that does not include oxygen through the showerhead and onto the substrate, thereby creating an annular gas region over an annular edge region of the substrate and an interior gas region over on an interior region of the substrate; the simultaneous flowing is not during a deposition of a material onto the substrate, and the annular gas region has an oxidization rate higher than the interior gas region.

Methods for filling gaps with dielectric material involve deposition using an atomic layer deposition (ALD) technique to fill a gap followed by deposition of a cap layer on the filled gap by a chemical vapor deposition (CVD) technique. The ALD deposition may be a plasma-enhanced ALD (PEALD) or thermal ALD (tALD) deposition. The CVD deposition may be plasma-enhanced CVD (PECVD) or thermal CVD (tCVD) deposition. In some embodiments, the CVD deposition is performed in the same chamber as the ALD deposition without intervening process operations. This in-situ deposition of the cap layer results in a high throughput process with high uniformity. After the process, the wafer is ready for chemical-mechanical planarization (CMP) in some embodiments.