C23C18/1607

Electroless copper plating polydopamine nanoparticles

Aqueous dispersions of artificially synthesized, mussel-inspired polydopamine nanoparticles were inkjet printed on flexible polyethylene terephthalate (PET) substrates. Narrow line patterns (4 m in width) of polydopamine resulted due to evaporatively driven transport (coffee ring effect). The printed patterns were metallized via a site-selective Cu electroless plating process at a controlled temperature (30 C.) for varied bath times. The lowest electrical resistivity value of the plated Cu lines was about 6 times greater than the bulk resistivity of Cu. This process presents an industrially viable way to fabricate Cu conductive fine patterns for flexible electronics at low temperature, and low cost.

Multi-Layer Circuit Board with Traces Thicker than a Circuit Board Layer
20200214144 · 2020-07-02 · ·

A multi-layer circuit board is formed multiple layers of a catalytic layer, each catalytic layer having an exclusion depth below a surface, where the cataltic particles are of sufficient density to provide electroless deposition in channels formed in the surface. A first catalytic layer has channels formed which are plated with electroless copper. Each subsequent catalytic layer is bonded or laminated to an underlying catalytic layer, a channel is formed which extends through the catalytic layer to an underlying electroless copper trace, and electroless copper is deposited into the channel to electrically connect with the underlying electroless copper trace. In this manner, traces may be formed which have a thickness greater than the thickness of a single catalytic layer.

ELECTROLESS COPPER PLATING POLYDOPAMINE NANOPARTICLES
20200157684 · 2020-05-21 ·

Aqueous dispersions of artificially synthesized, mussel-inspired polyopamine nanoparticles were inkjet printed on flexible polyethylene terephthalate (PET) substrates. Narrow line patterns (4 m in width) of polydopamine resulted due to evaporatively driven transport (coffee ring effect). The printed patterns were metallized via a site-selective Cu electroless plating process at a controlled temperature (30 C.) for varied bath times. The lowest electrical resistivity value of the plated Cu lines was about 6 times greater than the bulk resistivity of Cu. This process presents an industrially viable way to fabricate Cu conductive fine patterns for flexible electronics at low temperature, and low cost.

SURFACE FINISHES AND METHODS FOR PROVIDING SURFACE FINISHES TO A SUBSTRATE
20200122451 · 2020-04-23 ·

A method for providing a textured surface finish to a substrate includes providing an image having a contrast ratio; altering the image to increase the contrast ratio; determining an engraving profile for an ink transfer tool based on the contrast ratio of the image; etching the ink transfer tool in accordance with the engraving profile; coating the ink transfer tool with an ink; transferring the ink from the ink transfer tool to a substrate; applying a top coat to the substrate while the ink is set; and curing the ink and top coat on the substrate in an oven. The etching creates a plurality of wells in the ink transfer tool for holding the ink. The engraving profile is not identical to the altered image.

Stress patterning systems and methods for manufacturing free-form deformations in thin substrates

A device includes a substrate and a stressed layer disposed on a first surface of the substrate. The stressed layer includes: a first set of patterns having a predetermined geometry, size, and arrangement selected to control an equibiaxial stress field of the stressed layer, wherein the equibiaxial stress field varies in magnitude over the first surface of the substrate, and a second set of patterns etched into the first set of patterns and the substrate, the second set of patterns comprising a plurality of substantially parallel lines arranged to control at least a uniaxial stress field of the stressed layer, wherein the uniaxial stress field varies in magnitude over the first surface of the substrate.

Semiconductor devices comprising nickel— and copper—containing interconnects

A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

PLATING METHOD, PLATING APPARATUS AND RECORDING MEDIUM
20190267242 · 2019-08-29 ·

A substrate W having a non-plateable material portion 31 and a plateable material portion 32 formed on a surface thereof is prepared, and then, a catalyst is imparted selectively to the plateable material portion 32 by supplying a catalyst solution N1 onto the substrate W. Thereafter, a plating layer 35 is selectively formed on the plateable material portion 32 by supplying a plating liquid M1 onto the substrate W. A pH of the catalyst solution N1 is previously adjusted such that the plating layer 35 is suppressed from being precipitated on the non-plateable material portion 31 while being facilitated to be precipitated on the plateable material portion 32.

Method for manufacturing planar coil

Disclosed herein is a method for manufacturing a planar coil, the method including forming a base conductive layer on a base material, the base conductive layer including: a coil wiring portion having one end, other end, and first to third connecting positions, the second connecting position being closer to the other end compared with the first connecting position, the third connecting position being closer to the one end compared with the second connecting position; a power-feed wiring portion that connects the first connecting position with an external power source; and a connection wiring portion that short-circuits the second connecting position and the third connecting position; forming a wiring conductive layer on the base conductive layer by electrolytic plating by feeding power from the external power source; and removing the power-feed wiring portion and the connection wiring portion.

GAS SENSOR WITH SUPERLATTICE STRUCTURE

A gas sensor has a microstructure sensing element which comprises a plurality of interconnected units wherein the units are formed of connected graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

Method for producing patterned metallic coatings

A method for producing patterned metallic coatings includes an initiator composition having at least one active substance being added to a substrate. A precursor composition including at least one precursor compound for a metallic layer is applied to the initiator composition coating. A metallic layer is then deposited by the active substance. At least one composition is applied as an emulsion in order to obtain a patterning of the resultant metallic layer.