Patent classifications
C30B29/406
GROUP III NITRIDE STACK
There is provided a Group III nitride stack in which the concentration of an impurity in the buffer/channel layer of an HEMT is suppressed to a predetermined range. The Group III nitride stack includes a first layer comprising gallium nitride, and a second layer on the first layer, the second layer comprising a Group III nitride having a lower electron affinity than gallium nitride. The first layer includes a lower layer and an upper layer on the lower layer. The carbon concentration in the upper layer is lower than a carbon concentration in the lower layer, the hydrogen concentration in the upper layer is lower than a hydrogen concentration in the lower layer, the carbon concentration in the upper layer is 5×10.sup.16 cm.sup.−3 or less, and the hydrogen concentration in the upper layer is 1×10.sup.17 cm.sup.−3 or less.
POLYCRYSTALLINE CERAMIC SUBSTRATE AND METHOD OF MANUFACTURE
An engineered substrate structure includes a ceramic substrate having a front surface characterized by a plurality of peaks. The ceramic substrate includes a polycrystalline material. The engineered substrate structure also includes a planarization layer comprising a planarization layer material and coupled to the front surface of the ceramic substrate. The planarization layer defines fill regions filled with the planarization layer material between adjacent peaks of the plurality of peaks on the front surface of the ceramic substrate. The engineered substrate structure further includes a barrier shell encapsulating the ceramic substrate and the planarization layer, wherein the barrier shell has a front side and a back side, a bonding layer coupled to the front side of the barrier shell, a single crystal layer coupled to the bonding layer, and a conductive layer coupled to the back side of the barrier shell.
METHOD FOR MANUFACTURING NITRIDE CRYSTAL SUBSTRATE AND SUBSTRATE FOR CRYSTAL GROWTH
A high-quality nitride crystal substrate is manufactured, using a substrate for crystal growth with its diameter enlarged, the nitride crystal substrate including: a first step of preparing a substrate for crystal growth having a plurality of seed crystal substrates made of nitride crystals, arranged in a planar appearance, so that their main surfaces are parallel to each other and their lateral surfaces are in contact with each other, and a difference of a lattice constant between adjacent seed crystal substrates arbitrarily selected from a plurality of the seed crystal substrates is within 7×10.sup.−5 Å; and a second step of growing a crystal film on a ground surface belonging to the substrate for crystal growth.
METHOD OF MANUFACTURING GROUP-III NITRIDE CRYSTAL
A method of manufacturing a group-III nitride crystal includes: preparing a seed substrate; and supplying a group-III element oxide gas and a nitrogen element-containing gas at a supersaturation ratio (P.sup.o/P.sup.e) greater than 1 and equal to or less than 5, then, growing a group-III nitride crystal on the seed substrate, wherein the P.sup.o is a supply partial pressure of the group-III element oxide gas, and the P.sup.e is an equilibrium partial pressure of the group-III element oxide gas.
Method for Producing a Plurality of Semiconductor Chips and Semiconductor Chip
A method for producing a plurality of semiconductor chips and a semiconductor chip are disclosed. The method includes applying a mask material on a growth surface of a growth substrate, wherein the growth surface includes sapphire, patterning the mask material into a multiply-connected mask layer by introducing openings into the mask material, wherein the growth surface is exposed at the bottom of at least some of the openings, applying a semiconductor layer sequence on the mask layer and on the growth surface and singulating at least the semiconductor layer sequence into the plurality of semiconductor chips, wherein each semiconductor chip includes lateral dimensions and the lateral dimensions are large compared to an average distance of the openings to the nearest opening.
FABRICATING METHOD OF SEMI-POLAR GALLIUM NITRIDE
A method of fabricating semi-polar gallium nitride includes providing a silicon-on-insulator (SOI) substrate. The SOI substrate includes a substrate, a silicon oxide layer and a silicon substrate. The silicon substrate has (1,0,0) facets. The silicon oxide layer is disposed between the substrate and the silicon substrate. Later, a vapor etching process is performed to etch the (1,0,0) facets to form (1,1,1) facets. The vapor etching process is performed by disposing a nebulizer under the SOI substrate. The top surface of the silicon substrate faces the nebulizer. Later, the nebulizer turns etchant into mist to etch the (1,0,0) facets by the mist to form (1,1,1) facets. Finally, an epitaxial process is performed to grow a semi-polar gallium nitride layer on the (1,1,1) facets.
DEVICE INCLUDING SEMICONDUCTOR SUBSTRATE CONTAINING GALLIUM NITRIDE AND METHOD FOR PRODUCING THE SAME
A device includes a semiconductor substrate containing gallium nitride and having a crystal face inclined from 0.05° to 15° inclusive with respect to the c-plane. The semiconductor substrate includes an irregular portion on the crystal face, and the contact angle of pure water having a specific resistance of 18 MΩ.Math.cm or more on the surface of the irregular portion is 10° or less.
GROUP III NITRIDE SEMICONDUCTOR, AND METHOD FOR PRODUCING SAME
On an RAMO.sub.4 substrate containing a single crystal represented by the general formula RAMO.sub.4 (wherein R represents one or a plurality of trivalent elements selected from a group of elements including: Sc, In, Y, and a lanthanoid element, A represents one or a plurality of trivalent elements selected from a group of elements including: Fe(III), Ga, and Al, and M represents one or a plurality of divalent elements selected from a group of elements including: Mg, Mn, Fe(II), Co, Cu, Zn, and Cd), a buffer layer containing a nitride of In and a Group III element except for In is formed, and a Group III nitride crystal is formed on the buffer layer.
Wafer producing method
A wafer producing method for producing a hexagonal single crystal wafer from a hexagonal single crystal ingot includes a separation start point forming step of setting the focal point of a laser beam inside the ingot at a predetermined depth from the upper surface of the ingot, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam to the upper surface of the ingot while relatively moving the focal point and the ingot to thereby form a modified layer parallel to the upper surface of the ingot and cracks extending from the modified layer, thus forming a separation start point. In the separation start point forming step, the laser beam is applied to the ingot plural times with the focal point of the laser beam set at the modified layer previously formed, thereby separating the cracks from the modified layer.
PLANAR NONPOLAR GROUP III-NITRIDE FILMS GROWN ON MISCUT SUBSTRATES
A nonpolar III-nitride film grown on a miscut angle of a substrate. The miscut angle towards the <000-1> direction is 0.75° or greater miscut and less than 27° miscut towards the <000-1> direction. Surface undulations are suppressed and may comprise faceted pyramids. A device fabricated using the film is also disclosed. A nonpolar III-nitride film having a smooth surface morphology fabricated using a method comprising selecting a miscut angle of a substrate upon which the nonpolar III-nitride films are grown in order to suppress surface undulations of the nonpolar III-nitride films. A nonpolar III-nitride-based device grown on a film having a smooth surface morphology grown on a miscut angle of a substrate which the nonpolar III-nitride films are grown. The miscut angle may also be selected to achieve long wavelength light emission from the nonpolar film.