The invention relates to a surface element (1), intended for use as a floor, wall and/or ceiling surface element for a floor, wall and/or ceiling covering, having at least one carrier plate (2) and at least one functional layer (3), wherein the carrier plate (2) comprises a top side (5) facing a usable side (4) and an underside (7) opposite the top side (5) and facing the underground (6). According to the invention, it is provided that the functional layer (3) is provided underneath the carrier plate (2), and that the functional layer (3) is designed in such a way that, in the installed state, it projects beyond the side edge (10) of the side (8), in particular of the long side (9), on at least one side (8), especially on at least one long side (9).

A semiconductor integrated circuit is capable of electrically connecting to a capacitance variable capacitor whose electrostatic capacitance changes corresponding to an environmental change between a first and a second capacitances and determines whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed a reference capacitance value. The semiconductor integrated circuit includes a reference capacitor having a fixed electrostatic capacitance between the first capacitance and the second capacitance as the reference capacitance value; and an amplifier circuit, charging the capacitance variable capacitor via a first node and charging the reference capacitor via a second node corresponding to a clock signal, amplifying a potential difference between a potential of the first node and a potential of the second node, and outputting a binary determination signal indicating whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed the reference capacitance value based on the amplified potential difference.

A semiconductor integrated circuit is capable of electrically connecting to a capacitance variable capacitor whose electrostatic capacitance changes corresponding to an environmental change between a first and a second capacitances and determines whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed a reference capacitance value. The semiconductor integrated circuit includes a reference capacitor having a fixed electrostatic capacitance between the first capacitance and the second capacitance as the reference capacitance value; and an amplifier circuit, charging the capacitance variable capacitor via a first node and charging the reference capacitor via a second node corresponding to a clock signal, amplifying a potential difference between a potential of the first node and a potential of the second node, and outputting a binary determination signal indicating whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed the reference capacitance value based on the amplified potential difference.

To determine the temperature of a link capacitor (C) of a link converter (1) more accurately with less expenditure, a device and a method are described, in which the link capacitor (C) is modeled as a series interconnection of an equivalent capacitance (CS) and an equivalent series resistance (ESR), wherein a modeled capacitor current (i.sub.Cm) flows across the equivalent series resistance (ESR). A modeled capacitor power loss (P.sub.C), from which the capacitor temperature (T.sub.C) is determined by means of a specified temperature model, is calculated from the modeled capacitor current (i.sub.Cm,) and the value of the equivalent series resistance (ESR) by means of a first relationship of the form P.sub.C=f (i.sub.Cm, ESR). Direct measurement of the capacitor temperature (T.sub.C), of the capacitor current (i.sub.C), or of the capacitor power loss (P.sub.C) is not required. For example, a measurement of the capacitor voltage (u.sub.C) and a further calculation of the modeled capacitor current i.sub.Cm and finally of the capacitor power loss (P.sub.C) are sufficient. The method can be used for the monitoring and processing of the capacitor temperature (T.sub.C), particularly the switching-off of an element, preferably at least part of the link converter (1), when a maximum temperature, such as a preset maximum temperature, is exceeded. The method can also be used to determine the temporal progression of the capacitor temperature (T.sub.C(t)) and also to determine the remaining service life (RL) of the link capacitor (C) of a specified relationship, preferably by means of the Arrhenius formula.

To determine the temperature of a link capacitor (C) of a link converter (1) more accurately with less expenditure, a device and a method are described, in which the link capacitor (C) is modeled as a series interconnection of an equivalent capacitance (CS) and an equivalent series resistance (ESR), wherein a modeled capacitor current (i.sub.Cm) flows across the equivalent series resistance (ESR). A modeled capacitor power loss (P.sub.C), from which the capacitor temperature (T.sub.C) is determined by means of a specified temperature model, is calculated from the modeled capacitor current (i.sub.Cm,) and the value of the equivalent series resistance (ESR) by means of a first relationship of the form P.sub.C=f (i.sub.Cm, ESR). Direct measurement of the capacitor temperature (T.sub.C), of the capacitor current (i.sub.C), or of the capacitor power loss (P.sub.C) is not required. For example, a measurement of the capacitor voltage (u.sub.C) and a further calculation of the modeled capacitor current i.sub.Cm and finally of the capacitor power loss (P.sub.C) are sufficient. The method can be used for the monitoring and processing of the capacitor temperature (T.sub.C), particularly the switching-off of an element, preferably at least part of the link converter (1), when a maximum temperature, such as a preset maximum temperature, is exceeded. The method can also be used to determine the temporal progression of the capacitor temperature (T.sub.C(t)) and also to determine the remaining service life (RL) of the link capacitor (C) of a specified relationship, preferably by means of the Arrhenius formula.

A power device temperature monitor is provided. The power device temperature monitor includes a power device having a control terminal and an output terminal, where the output terminal is configured to output a current as directed by a voltage of the control terminal. The power device temperature monitor includes an inductor coupled to the output terminal of the power device and an amplifier coupled to the inductor. The power device temperature monitor includes a computing device that receives an output of the amplifier, the computing device is configured to derive a temperature of the power device based upon the output of the amplifier.

A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area on a surface of a substrate during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device, wherein at least one electrical device is provided on the surface of the substrate and the at least one electrical device includes a temperature sensor. The acoustic wave device protection structure comprising: a metal covering layer, having a concave surface and a bottom rim, the bottom rim connected to the acoustic wave device and forming at least one opening between the bottom rim and the acoustic wave device, and the concave surface covering over the resonant area to form a cavity between the concave surface and the resonant area.

A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area on a surface of a substrate during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device, wherein at least one electrical device is provided on the surface of the substrate and the at least one electrical device includes a temperature sensor. The acoustic wave device protection structure comprising: a metal covering layer, having a concave surface and a bottom rim, the bottom rim connected to the acoustic wave device and forming at least one opening between the bottom rim and the acoustic wave device, and the concave surface covering over the resonant area to form a cavity between the concave surface and the resonant area.

A pyroelectric device, comprising a plurality of layers of a polar dielectric material having a pyroelectric coefficient, p, wherein each layer exhibits pyroelectric properties; a plurality of conductive electrodes, wherein each conductive electrode is substantially in contact with at least a portion of one surface of a respective at least one of said plurality of layers of polar dielectric material, wherein said electrodes are electrically connected in a parallel configuration as to form a series of capacitors comprised of said plurality of layers of polar dielectric material and plurality of conductive electrodes.

A pyroelectric device, comprising a plurality of layers of a polar dielectric material having a pyroelectric coefficient, p, wherein each layer exhibits pyroelectric properties; a plurality of conductive electrodes, wherein each conductive electrode is substantially in contact with at least a portion of one surface of a respective at least one of said plurality of layers of polar dielectric material, wherein said electrodes are electrically connected in a parallel configuration as to form a series of capacitors comprised of said plurality of layers of polar dielectric material and plurality of conductive electrodes.