A BMU, which is a battery management unit, includes a current measuring unit that measures a current charged to and discharged from a battery; a voltage measuring unit that measures a voltage of the battery during measurement of the current by the current measuring unit; a BPF processing unit that extracts a component in a prescribed frequency band, of the current measured by the current measuring unit; a BPF processing unit that extracts a component in the prescribed frequency band, of the voltage measured by the voltage measuring unit; and an impedance calculating unit that calculates an impedance of the battery using the extracted current component and voltage component.

An apparatus and test method for simulating spark discharge of a high-voltage electrostatic precipitator are provided. The simulation apparatus includes a pulse power supply configured to provide a test voltage, an anode cylinder configured to simulate an anode of a precipitator, a cathode rod configured to simulate a cathode of the precipitator, a pulse capacitor unit configured to simulate an electrode capacitor of the precipitator, an insulating support configured to hang the cathode rod, a voltage divider configured to measure an electrode voltage, and a grounded current sampling unit configured to measure grounded current. The simulation apparatus simulates a discharge process of the high-voltage electrostatic precipitator to measure discharge characteristic parameters such as discharge current and discharge energy of the high-voltage electrostatic precipitator. In this way, characteristics of spark discharge of the precipitator under different load conditions are simulated.

A method for detecting the presence of a receiver in an inductively coupled power transfer system having a transmitter and receiver. The method includes switching on a transmitter converter at a first frequency, measuring the inrush current and determining whether there is a receiver present. In another method, the inrush current is measured for a range of transmitter frequencies, and the variation in current is used to determine where there is a receiver present. In another method, the inrush current is measured when there is a change in voltage in the transmitter, and the variation in current is used to determine where there is a receiver present. In another method, the current supplied to the transmitter converter is measured over two transmitter frequencies, and the variation in current is used to determine where there is a receiver present. In another method, the current supplied to the transmitter converter is measured over two transmitter voltages, and the variation in current is used to determine where there is a receiver present.

A method for detecting the presence of a receiver in an inductively coupled power transfer system having a transmitter and receiver. The method includes switching on a transmitter converter at a first frequency, measuring the inrush current and determining whether there is a receiver present. In another method, the inrush current is measured for a range of transmitter frequencies, and the variation in current is used to determine where there is a receiver present. In another method, the inrush current is measured when there is a change in voltage in the transmitter, and the variation in current is used to determine where there is a receiver present. In another method, the current supplied to the transmitter converter is measured over two transmitter frequencies, and the variation in current is used to determine where there is a receiver present. In another method, the current supplied to the transmitter converter is measured over two transmitter voltages, and the variation in current is used to determine where there is a receiver present.

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

Maximum voltage detection in a power management circuit is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. The voltage processing circuit includes a maximum signal detector circuit configured to generate a windowed time-variant target voltage that is higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. In this regard, the windowed time-variant target voltage can tolerate a certain amount of group delay within the group delay tolerance window(s).

Maximum voltage detection in a power management circuit is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. The voltage processing circuit includes a maximum signal detector circuit configured to generate a windowed time-variant target voltage that is higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. In this regard, the windowed time-variant target voltage can tolerate a certain amount of group delay within the group delay tolerance window(s).